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[DSP program2812dsp-Sci

Description: 这是一个基于DSP2812的串口通讯下位机程序,通过该程序可以实现和上位机通讯,将上位机的数据读入,设置电机的转矩和转速.挺好的一个程序,供参考.-This is a serial communication based on the DSP2812-bit machine under the procedures, the adoption of the procedures can be achieved and the host computer communications, will host computer to read data, set the motor torque and speed. A very good procedures for reference.
Platform: | Size: 67584 | Author: 高志安 | Hits:

[DSP programDSP2812FIFO

Description: DSP上实现 软件FIFO队列 提高SCI的数据缓冲能力-DSP to achieve the software improve the SCI data FIFO queue buffering capacity
Platform: | Size: 5120 | Author: 王易龙 | Hits:

[DSP programDSP_2812_SCI_232

Description: DSP2812串口通信编程,利用FIFO中断接收数据以及利用查询方式发送数据-TMS320F2812SCI code
Platform: | Size: 389120 | Author: 黄晓军 | Hits:

[DSP programSCI_485

Description: 文档时我最近编写的DSP的SCI通信,采用的485,通信速率达到1.5Mb/s,采用的FIFO功能。-I recently prepared a document of the SCI communication DSP, using the 485, communication rates up to 1.5Mb/s, using the FIFO function.
Platform: | Size: 2578432 | Author: 白建成 | Hits:

[DSP programF2812_SCI03

Description: F2812 SCI (CCS3.3开发环境下)采用收发FIFO中断方式与PC机串口调试助手实现收发数据。 功 能:使用SCIA模块和PC机进行串口通信,等待PC机上的串口调试软件向DSP发送"hellodsp",DSP接收到上位机发送的数据之后,将这些数据发回PC机,显示在串口调试软件中。 说 明:本实验中SCIA模块的发送和接收采用FIFO的中断方式实现,空闲线模式波特率为19200,通信数据格式为1位停止位,8位数据位,无校验位-F2812 SCI receive and send FIFO interrupt mode using the PC serial port debugging assistant the transmitting and receiving data. Function: Using SCIA module and the PC serial port communication, waiting for the PC s serial port debug software to the DSP to send "hellodsp", DSP receives a host computer to send the data, these data back to a PC, displayed on the serial debugging software . Description: This experiment SCIA module to send and receive using the FIFO interrupt mode to achieve, idle-line mode at 19200 baud, communication data format is 1 stop bit, 8 data bits, no parity
Platform: | Size: 345088 | Author: 奋斗不止 | Hits:

[VHDL-FPGA-Verilogmyuart

Description: 使用verilog语言编写的异步串口模块,带有16级深的FIFO,它与DSP28335的SCI相似,可以帮助初学者更快地理解FPGA和DSP的硬件结构和编程思路-Use verilog language of asynchronous serial port module, FIFO with deep level 16, it was similar with DSP28335 SCI, can help beginners to understand faster the FPGA and DSP hardware structure and programming ideas
Platform: | Size: 492544 | Author: 夏小保 | Hits:

[DSP programscibreakfifo

Description: DSP F2812 sci的FIFO中断模式收发数据-DSP F2812 sci send and receive data in the FIFO interrupt mode
Platform: | Size: 286720 | Author: 李镇海 | Hits:

[DSP programSCI-FIFO--(RS485)

Description: 利用DSP的开发工具CCS实现了RS485总线的数据收发功能,并以此和触摸屏通讯-DSP RS485 HMI
Platform: | Size: 415744 | Author: 吴振熊 | Hits:

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