Description: 通信系统中，信号捕获和同步的数字锁相环的MATLAB仿真程序-communications systems, signal acquisition and synchronization of digital PLL MATLAB simulation program Platform: |
Size: 122777 |
Author:zlin |
Hits:
Description: PLL是数字锁相环设计源程序, 其中, Fi是输入频率(接收数据), Fo(Q5)是本地输出频率. 目的是从输入数据中提取时钟信号(Q5), 其频率与数据速率一致, 时钟上升沿锁定在数据的上升和下降沿上；顶层文件是PLL.GDF-digital phase-locked loop PLL design source, in which Fi is the input frequency (receive data), Fo (Q5) is the local output frequency. Objective is to extract data input clock signal (Q5), its frequency and data rate line, the clock rising edge of the lock data the rising and falling edge; top-level document is PLL.GDF Platform: |
Size: 124928 |
Author:于洪彪 |
Hits:
Description: 通信系统中，信号捕获和同步的数字锁相环的MATLAB仿真程序-communications systems, signal acquisition and synchronization of digital PLL MATLAB simulation program Platform: |
Size: 122880 |
Author:zlin |
Hits:
Description: 数字锁相环，采用costas环的数字形式，实现跟踪载波相位，-Digital phase-locked loop, using the digital form costas loop to achieve carrier phase tracking, Platform: |
Size: 1024 |
Author:lily |
Hits:
Description: MIT的一个数字频综源代码，包括cadence的，CPPSIM（MIT做的PLL的设计软件）-MIT, a digital frequency synthesizer source code, including the cadence of, CPPSIM (MIT make the PLL design software) Platform: |
Size: 27648 |
Author:hqh |
Hits:
Description: This project allows you to learn communication systems in greater depth. It contains the Simulink files (*.mdl) which are block design files of various communication systems such as AM, DSB-SC, FM, PLL, Data Acquisition, Digital Data Transmission, PCM and Delta Modulation.
The idea here is to implement experiments of a traditional communication lab using Simulink.
Most of the block diagrams are self explanatory. More information on the systems and their implementation can be found in the word documents included in the lab directories-This project allows you to learn communication systems in greater depth. It contains the Simulink files (*. mdl) which are block design files of various communication systems such as AM, DSB-SC, FM, PLL, Data Acquisition, Digital Data Transmission, PCM and Delta Modulation. The idea here is to implement experiments of a traditional communication lab using Simulink.Most of the block diagrams are self explanatory. More information on the systems and their implementation can be found in the word documents included in the lab directories Platform: |
Size: 2468864 |
Author:haibak |
Hits:
Description: 本人写的数字锁相环，有模拟数据，学习锁相环很好的材料。参考书“数字锁相环路原理与应用”编写。-I write the digital phase-locked loop, have simulated data, a good phase-locked loop learning materials. Reference book Platform: |
Size: 1024 |
Author:杨广 |
Hits:
Description: 使用改进的COSTAS环实现锁相环（PLL），应用于高动态的数字化接收系统-COSTAS Central improved to achieve phase-locked loop (PLL), used in high dynamic digital reception system Platform: |
Size: 14336 |
Author:张景英 |
Hits:
Description: 锁相环问题的仿真，可以解决数字锁相环的仿真问题-Phase-locked loop simulation problem, can solve the problem of digital phase-locked loop simulation Platform: |
Size: 1024 |
Author:wangxinyi |
Hits:
Description: 包括了对不同通信系统的simulink仿真，如AM, DSB-SC, FM, PLL, Data Acquistion, Digital Data Transmission, PCM and Delta Modulation。通过这些可以帮助用户对通信仿真有更深的理解。-This project allows you to learn the communication systems in greater depth by giving you
the reins to play with it ! It contains the simulink files (*.mdl) which are block design
files of various communication systems such as AM, DSB-SC, FM, PLL, Data Acquisition, Digital
Data Transmission, PCM and Delta Modulation. Platform: |
Size: 2022400 |
Author:yinwenyi |
Hits:
Description: This tutorial starts with a simple conceptual model of an analog Phase-Locked Loop (PLL). Through elaboration it ends at a model of an all digital and fixed-point phase-locked loop. The final model can serve a starting point for code generation (both ANSI C or synthesizable HDL).
The step-wise elaboration of the model illustrates how Simulink® forms the basis a model-based design where continuous verification of the model reduces errors.
-This tutorial starts with a simple conceptual model of an analog Phase-Locked Loop (PLL). Through elaboration it ends at a model of an all digital and fixed-point phase-locked loop. The final model can serve a starting point for code generation (both ANSI C or synthesizable HDL).
The step-wise elaboration of the model illustrates how Simulink® forms the basis a model-based design where continuous verification of the model reduces errors.
Platform: |
Size: 399360 |
Author:张骅 |
Hits:
Description: 基于Matlab的数字锁相环的仿真设计，一篇毕业论文，对数字和模拟锁相环进行了详细的分析和仿真-Matlab-based simulation of digital PLL design, a thesis on digital and analog phase-locked loop for a detailed analysis and simulation Platform: |
Size: 199680 |
Author:张鑫 |
Hits:
Description: 基于Matlab仿真的数字锁相环的设计进行了详细的分析和模拟，数字和模拟锁相环的论文-Matlab-based simulation of digital PLL design, a thesis on digital and analog phase-locked loop for a detailed analysis and simulation Platform: |
Size: 2048 |
Author:xufeng |
Hits:
Description: 封装的matlab程序，实现数字锁相环的功能函数(Encapsulated matlab program to implement the function function of the digital PLL) Platform: |
Size: 1024 |
Author:MFC_B
|
Hits:
Description: 基于matlab的数字pll实现，鉴相器，滤波器以及压控震荡器组成，具备良好的锁相功能，适合入门学习(Digital PLL based on MATLAB, phase detector, filter and voltage controlled oscillator, phase lock function has good, suitable for beginners to learn) Platform: |
Size: 17408 |
Author:qiya2 |
Hits:
Search - Digital PLL MATLAB