Search - Digital PLL MATLAB

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[Other resource] 数字锁相环dll_code DL : 1: 通信系统中，信号捕获和同步的数字锁相环的MATLAB仿真程序-communications systems, signal acquisition and synchronization of digital PLL MATLAB simulation program
Update : 2008-10-13 Size : 119.9kb Publisher : zlin
[VHDL-FPGA-Verilog] 数字锁相环 DL : 0: PLL是数字锁相环设计源程序, 其中, Fi是输入频率(接收数据), Fo(Q5)是本地输出频率. 目的是从输入数据中提取时钟信号(Q5), 其频率与数据速率一致, 时钟上升沿锁定在数据的上升和下降沿上；顶层文件是PLL.GDF-digital phase-locked loop PLL design source, in which Fi is the input frequency (receive data), Fo (Q5) is the local output frequency. Objective is to extract data input clock signal (Q5), its frequency and data rate line, the clock rising edge of the lock data the rising and falling edge; top-level document is PLL.GDF
Update : 2025-02-19 Size : 122kb Publisher : 于洪彪
[Post-TeleCom sofeware systems] 数字锁相环dll_code DL : 0: 通信系统中，信号捕获和同步的数字锁相环的MATLAB仿真程序-communications systems, signal acquisition and synchronization of digital PLL MATLAB simulation program
Update : 2025-02-19 Size : 120kb Publisher : zlin
[matlab] DPLL1lp DL : 0: 频带数字通信中，频带一阶锁相环simulink模型-band digital communications, a frequency band PLL Simulink model
Update : 2025-02-19 Size : 8kb Publisher : rossi
[Applications] dpll DL : 1: 数字锁相环，采用costas环的数字形式，实现跟踪载波相位，-Digital phase-locked loop, using the digital form costas loop to achieve carrier phase tracking,
Update : 2025-02-19 Size : 1kb Publisher : lily
[Communication-Mobile] wb_digital_synthesizer.tar DL : 0: MIT的一个数字频综源代码，包括cadence的，CPPSIM（MIT做的PLL的设计软件）-MIT, a digital frequency synthesizer source code, including the cadence of, CPPSIM (MIT make the PLL design software)
Update : 2025-02-19 Size : 27kb Publisher : hqh
[matlab] Matlab_model DL : 0: 在MATLAB环境下，对全数字锁相环的仿真，分析锁相环的性能参数-In the MATLAB environment, to all-digital phase-locked loop simulation, analysis of the performance parameters of phase-locked loop
Update : 2025-02-19 Size : 238kb Publisher : 梁大法
[ELanguage] simulink_labs DL : 0: This project allows you to learn communication systems in greater depth. It contains the Simulink files (*.mdl) which are block design files of various communication systems such as AM, DSB-SC, FM, PLL, Data Acquisition, Digital Data Transmission, PCM and Delta Modulation. The idea here is to implement experiments of a traditional communication lab using Simulink. Most of the block diagrams are self explanatory. More information on the systems and their implementation can be found in the word documents included in the lab directories-This project allows you to learn communication systems in greater depth. It contains the Simulink files (*. mdl) which are block design files of various communication systems such as AM, DSB-SC, FM, PLL, Data Acquisition, Digital Data Transmission, PCM and Delta Modulation. The idea here is to implement experiments of a traditional communication lab using Simulink.Most of the block diagrams are self explanatory. More information on the systems and their implementation can be found in the word documents included in the lab directories
Update : 2025-02-19 Size : 2.35mb Publisher : haibak
[VHDL-FPGA-Verilog] myDPll DL : 0: 本人写的数字锁相环，有模拟数据，学习锁相环很好的材料。参考书“数字锁相环路原理与应用”编写。-I write the digital phase-locked loop, have simulated data, a good phase-locked loop learning materials. Reference book
Update : 2025-02-19 Size : 1kb Publisher : 杨广
[Other] costas_loop DL : 0: 使用改进的COSTAS环实现锁相环（PLL），应用于高动态的数字化接收系统-COSTAS Central improved to achieve phase-locked loop (PLL), used in high dynamic digital reception system
Update : 2025-02-19 Size : 14kb Publisher : 张景英
[Communication-Mobile] PLL DL : 0: 锁相环问题的仿真，可以解决数字锁相环的仿真问题-Phase-locked loop simulation problem, can solve the problem of digital phase-locked loop simulation
Update : 2025-02-19 Size : 1kb Publisher : wangxinyi
[matlab] simulink_labs DL : 1: 包括了对不同通信系统的simulink仿真，如AM, DSB-SC, FM, PLL, Data Acquistion, Digital Data Transmission, PCM and Delta Modulation。通过这些可以帮助用户对通信仿真有更深的理解。-This project allows you to learn the communication systems in greater depth by giving you the reins to play with it ! It contains the simulink files (*.mdl) which are block design files of various communication systems such as AM, DSB-SC, FM, PLL, Data Acquisition, Digital Data Transmission, PCM and Delta Modulation.
Update : 2025-02-19 Size : 1.93mb Publisher : yinwenyi
[matlab] PhaseLockedLoop DL : 0: This tutorial starts with a simple conceptual model of an analog Phase-Locked Loop (PLL). Through elaboration it ends at a model of an all digital and fixed-point phase-locked loop. The final model can serve a starting point for code generation (both ANSI C or synthesizable HDL). The step-wise elaboration of the model illustrates how Simulink® forms the basis a model-based design where continuous verification of the model reduces errors. -This tutorial starts with a simple conceptual model of an analog Phase-Locked Loop (PLL). Through elaboration it ends at a model of an all digital and fixed-point phase-locked loop. The final model can serve a starting point for code generation (both ANSI C or synthesizable HDL). The step-wise elaboration of the model illustrates how Simulink® forms the basis a model-based design where continuous verification of the model reduces errors.
Update : 2025-02-19 Size : 390kb Publisher : 张骅
[VHDL-FPGA-Verilog] PLL DL : 0: 用VHDL和matlab编写的数字锁相环电路。-Matlab with VHDL and digital phase-locked loop circuit prepared.
Update : 2025-02-19 Size : 21kb Publisher : 水淼
[matlab] Matlabpll DL : 0: 基于Matlab的数字锁相环的仿真设计，一篇毕业论文，对数字和模拟锁相环进行了详细的分析和仿真-Matlab-based simulation of digital PLL design, a thesis on digital and analog phase-locked loop for a detailed analysis and simulation
Update : 2025-02-19 Size : 195kb Publisher : 张鑫
[Software Engineering] simulink DL : 0: simulink的数字调制解调仿真。以simulink为基础平台，对2ASK、2FSK、2PSK信号的仿真-Digital modulation and demodulation simulink simulation. The simulink-based platform, 2ASK, 2FSK, 2PSK Signal Simulation
Update : 2025-02-19 Size : 665kb Publisher : 方方
[matlab] Matlab-based-simulation-PLL-design- DL : 0: 基于Matlab仿真的数字锁相环的设计进行了详细的分析和模拟，数字和模拟锁相环的论文-Matlab-based simulation of digital PLL design, a thesis on digital and analog phase-locked loop for a detailed analysis and simulation
Update : 2025-02-19 Size : 2kb Publisher : xufeng
[matlab] PLL_continious DL : 0: 数字锁相环，matlab仿真模型，用PID实现-digital PLL,MATLAB simulation module
Update : 2025-02-19 Size : 11kb Publisher : 刘伟
[matlab] pll DL : 0: 封装的matlab程序，实现数字锁相环的功能函数(Encapsulated matlab program to implement the function function of the digital PLL)
Update : 2025-02-19 Size : 1kb Publisher : MFC_B
[matlab] pll DL : 0: 基于matlab的数字pll实现，鉴相器，滤波器以及压控震荡器组成，具备良好的锁相功能，适合入门学习(Digital PLL based on MATLAB, phase detector, filter and voltage controlled oscillator, phase lock function has good, suitable for beginners to learn)
Update : 2025-02-19 Size : 17kb Publisher : qiya2

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