Search - Direct Digital Frequency Synthesizer vhdl

[Other resource] DDS_sin

Description: 用VHDL语言实现DDS直接数字频率合成器的设计，采用正弦RAM表，可实现频率可控的正弦数字信号，编译、仿真通过。-VHDL DDS Direct Digital Frequency Synthesizer Design using sinusoidal RAM table achieve controllable frequency sinusoidal digital signal, compile, through simulation.
Platform: | Size: 8747 | Author: sarahyu | Hits:

[VHDL-FPGA-Verilog] DDS_sin

[VHDL-FPGA-Verilog] EDAdesign(3)

Description: 该文件中是关于一些VHDL许多编程实例以及源码分析，希望对VHDL爱好者有用。卷3包括车载DVD位控系统、直接数字频率合成器、图像边缘检测器、等精度数字频率计、出租车计费系统的设计与分析-The document is on a number of VHDL source code in many programming examples and analysis, in the hope that useful VHDL enthusiasts. Car DVD Volume 3 includes digital control system, direct digital frequency synthesizer, image edge detector, such as precision digital frequency meter, taxi Accounting System Design and Analysis
Platform: | Size: 4392960 | Author: shengm1 | Hits:

[VHDL-FPGA-Verilog] FPGAddfs

Description: 基于FPGA的直接数字频率合成器的设计与实现.-FPGA-Based Direct Digital Frequency Synthesizer Design and Implementation.
Platform: | Size: 222208 | Author: 周真 | Hits:

[VHDL-FPGA-Verilog] vhdlddfs

Description: 用VHDL设计直接数字频率合成器-VHDL design with direct digital frequency synthesizer
Platform: | Size: 190464 | Author: 周真 | Hits:

[VHDL-FPGA-Verilog] dds

Description: 直接数字频率合成器，基于vhdl语言，在qartus II上实现，下载调试成功-Direct digital frequency synthesizer, based on the VHDL language, in qartus II achieved a successful download debugging
Platform: | Size: 316416 | Author: 浮云 | Hits:

[Wavelet] DDS

Description: 利用EDA技术和FPGA在UP3开发板上实现直接数字频率综合器的设计。实验中加入了相位控制字PWORD，用以控制相位偏移量的前四位，将相位偏移量加到ROM地址总线上，从而引起从ROM中取得的正弦信号的偏移，实现移相信号发生器的移相功能。实验中还加入了LCD显示功能，通过LCD显示模块器件，用LCD显示正弦信号的频率，所显示的频率也是由频率字控制的。LCD的驱动原理同上次实验。-The use of EDA technology and FPGA development in the UP3 board direct digital frequency synthesizer design. Experiment by adding a phase control word PWORD, to control the phase offset of the top four will be added to the phase offset ROM address bus, thereby causing ROM obtained from the sinusoidal signal offset, shifted believe realize its phase-shifting function generator. Experiments have also joined the LCD display, LCD display module through the device, with LCD display the frequency of sinusoidal signal, as shown by the frequency of word frequency control. LCD driving principles with the previous experiment.
Platform: | Size: 1225728 | Author: Emma | Hits:

[VHDL-FPGA-Verilog] DDS

Description: 《DDS原理简介(中文)》DDS即直接数字频率合成器，原理及系统设计实现- DDS Principle Introduction (Chinese) DDS direct digital frequency synthesizer, the principle and system design to achieve
Platform: | Size: 454656 | Author: 范田田 | Hits:

[VHDL-FPGA-Verilog] FPGA_signal_general

Description: 摘要：介绍了直接数字频率合成 (DDS) 技术的基本原理，给出了基于Altera公司FPGA器件的一个三相正弦信号发生器的设计方案，同时给出了其软件程序和仿真结果。仿真结果表明：该方法生成的三相正弦信号具有对称性好、波形失真小、频率精度高等优点，且输出频率可调。关键词：直接数字频率合成；现场可编程门阵列；FPGA；三相正弦信号-Abstract: Direct Digital Synthesis (DDS) technology, the basic principles are given Altera-based FPGA devices the company a three-phase sinusoidal signal generator design program, at the same time give its software programs and simulation results. The simulation results show that: the method to generate three-phase sinusoidal signal with good symmetry, waveform distortion small, the frequency of high precision, and adjustable output frequency. Key words: direct digital synthesizer field programmable gate array FPGA three-phase sinusoidal signal
Platform: | Size: 101376 | Author: 赵文 | Hits:

[Other] e

Description: 《EDA技术实用教程》实验选编专题一：计数分频器设计 4 专题二：存储器定制 7 实验一：快速乘法器电路设计 11 实验二：高速数字相关器设计 17 实验三：TLC5510高速A/D转换器控制 21 实验四：直接数字频率合成器（DDFS）设计 23 实验五：基于直接数字频率合成技术的任意波形发生器-" EDA technology practical course" Selected experimental one topic: the design count crossovers feature 4 2: 7 experiment a custom memory: Fast multiplier circuit design of 11 experiments II: the design of high-speed digital correlator 17, the experiment three: TLC5510 high-speed A/D converter control 21 of the experiment four: Direct Digital Frequency Synthesizer (DDFS) experimental design, 23 5: Based on Direct Digital Synthesis technology, arbitrary waveform generator
Platform: | Size: 2693120 | Author: 耿守浩 | Hits:

[VHDL-FPGA-Verilog] FPGA-DDC

Description: 基于FPGA的直接数字频率合成器的设计和实现。-FPGA-Based Direct Digital Frequency Synthesizer Design and Implementation.
Platform: | Size: 100352 | Author: 孙新荣 | Hits:

[Technology Management] dds9851

Description: 本文主要介绍的是采用直接数字频率合成的短波信号发生器，它主要以微电脑控制部分、直接数字频率合成（DDS）部分、数字锁相环频率合成部分、背光液晶显示部分、功率放大部分等组成。该软件系统采用菜单形式进行操作，操作方便明了，增加了很多功能。它通过启动DDS后，把内存缓存区的数据送到DDS后输出相应的频率，并把数据转换为BCD码，送到液晶显示器进行显示。该系统输出稳定度、精度极高，适用于当代的尖端的通信系统和精密的高精度仪器。-This paper describes the use of direct digital frequency synthesis of short-wave signal generator, which is part of a micro-computer control, Direct Digital Synthesis (DDS) of the digital part of PLL frequency synthesizer, backlit liquid crystal display of the power amplifier, etc. composition. The menu system uses the form of software to operate, easy to operate and clear, increase in the number of features. DDS through start after the memory cache after the data to the DDS output corresponding frequency, and the data is converted to BCD code to the LCD display. The output of the system stability, high precision for cutting-edge contemporary and sophisticated communication systems high-precision instruments
Platform: | Size: 466944 | Author: xiang | Hits:

[VHDL-FPGA-Verilog] ddfsdemo

Description: 直接数字频率合成器（Direct Digital Frequency Synthesizer：DDFS）的VHDL程序,开发环境是QuartusII,系统时钟为50MHz，由PLL产生DDFS的工作时钟166.67MHz,地址位宽为24位，频率字为20，相位字为10，RAM用于存储查找表，其地址位宽为10，数据位宽为8。-Direct Digital Frequency Synthesizer ( DDFS) of the VHDL program, the development environment is QuartusII, the system clock to 50MHz, the work of DDFS generated by PLL clock 166.67MHz, address bit-width of 24-bit frequency word is 20, phase word for 10, RAM used to store look-up table, its address is 10 bits wide, the data is 8 bits wide.
Platform: | Size: 647168 | Author: 力文 | Hits:

[VHDL-FPGA-Verilog] ddfs

Description: 直接数字频率合成器，整个工程文件都在，仿真也有，直接就能用。-Direct digital frequency synthesizer, the entire project file are in the simulation is also directly be able to use.
Platform: | Size: 478208 | Author: 虎 | Hits:

[Software Engineering] zok

Description: 介绍直接数字频率合成器的论文，非常的详细，还有VHDL源代码-Introduction of Direct Digital Frequency Synthesizer papers, very detailed, as well as VHDL source code
Platform: | Size: 676864 | Author: 洪依 | Hits:

[VHDL-FPGA-Verilog] Study_on_Key_Technologies_of_n4-DQPSK_Modulation_a

Description: 本文首先研究可4一DQPsK调制解调系统中调制部分的基本原理和各个模块的设计方案，重点研究成形滤波器和直接数字频率合成器 (DireetoigitalFrequeneySynihesis，简称DDS)，并针对各个关键模块算法进行matlab设计仿真，展示仿真结果。其次，研究调制解调系统解调部分的基本原理和各个模块的设计方案，重点研究差分解调，数字下变频和位同步算法，也针对其各个关键模块进行算法的Matlab设计仿真。然后用Matlab对整个系统进行理论仿真，得出结论。在此基础上，采用超高速集成电路硬件描述语言(VeryHighspeedxntegatedeireuitHardware DescriptionLan即age，简称VHDL)在Altera公司 Quartusll7.0开发环境下设计并实现各个功能块，通过仿真来证明功能正确性。再次，用 Protel99SE进行印制电路板(Prinicircuitboard，简称PcB)设计，从原理图到封装，再到布局布线。焊接调试完毕后，将设计好的程序下载至FPGA主芯片。最后观察信号时域波形、星座图、眼图。本系统信源输入符号速率100kbPs，调制中频10MHz。测试结果验证系统的正确性，实现了从数字基带到中频的可4一DQPSK调制解调系统-This study is the first 4 1 DQPsK modem modulation system, part of the basic principles and design of each module, focusing on shaping filter and a direct digital frequency synthesizer (DireetoigitalFrequeneySynihesis, referred to as DDS), and to address all the key modules algorithm matlab design simulation to show simulation results. Second, the study of modulation and demodulation system demodulation part of the basic principles and design of each module, focusing on differential demodulation, digital down conversion and bit synchronization algorithm, but also for its various key module of the Matlab algorithm design and simulation. Then use the Matlab simulation of the entire system theory, reach a conclusion. On this basis, , Using ultra-high speed integrated circuit hardware description language (VeryHighspeedxntegatedeireuitHardware DescriptionLan that age, referred to as VHDL) in the Altera Corporation Quartusll7.0 development environment to design and implement the variou
Platform: | Size: 5457920 | Author: cai | Hits:

Category

Source Code

Web/Internet

Develop Tools

Document

Other

Search in results

OS

Platform

Language

File Type

Search list

[Other resource] DDS_sin

[VHDL-FPGA-Verilog] DDS_sin

[VHDL-FPGA-Verilog] EDAdesign(3)

[VHDL-FPGA-Verilog] FPGAddfs

[VHDL-FPGA-Verilog] vhdlddfs

[VHDL-FPGA-Verilog] dds

[Wavelet] DDS

[VHDL-FPGA-Verilog] DDS

[VHDL-FPGA-Verilog] FPGA_signal_general

[Other] e

[VHDL-FPGA-Verilog] FPGA-DDC

[Technology Management] dds9851

[VHDL-FPGA-Verilog] ddfsdemo

[VHDL-FPGA-Verilog] ddfs

[Software Engineering] zok

[VHDL-FPGA-Verilog] Study_on_Key_Technologies_of_n4-DQPSK_Modulation_a

[VHDL-FPGA-Verilog] dds_xu

[VHDL-FPGA-Verilog] FPGA-VHDL-DDS

[VHDL-FPGA-Verilog] DDS-Based-on-VHDL

[VHDL-FPGA-Verilog] dds

CodeBus www.codebus.net