Description: Direct Digital Frequency Synthesizer ( DDFS) of the VHDL program, the development environment is QuartusII, the system clock to 50MHz, the work of DDFS generated by PLL clock 166.67MHz, address bit-width of 24-bit frequency word is 20, phase word for 10, RAM used to store look-up table, its address is 10 bits wide, the data is 8 bits wide.
- [sji] - Abstract；The frequency synthesis technol
- [uEyeCSharp] - CSharp developed with IDS s utility and
- [fullsine] - This is a code for sine wave generation
File list (Check if you may need any files):
ddfsdemo
........\db
........\..\altsyncram_cvn1.tdf
........\..\ddfsdemo.analyze_file.qmsg
........\..\ddfsdemo.asm.qmsg
........\..\ddfsdemo.atom.rvd
........\..\ddfsdemo.cbx.xml
........\..\ddfsdemo.cmp.bpm
........\..\ddfsdemo.cmp.cdb
........\..\ddfsdemo.cmp.ecobp
........\..\ddfsdemo.cmp.hdb
........\..\ddfsdemo.cmp.logdb
........\..\ddfsdemo.cmp.qrpt
........\..\ddfsdemo.cmp.rdb
........\..\ddfsdemo.cmp.tdb
........\..\ddfsdemo.cmp0.ddb
........\..\ddfsdemo.cmp_bb.cdb
........\..\ddfsdemo.cmp_bb.hdb
........\..\ddfsdemo.cmp_bb.logdb
........\..\ddfsdemo.cmp_bb.rcf
........\..\ddfsdemo.dbp
........\..\ddfsdemo.db_info
........\..\ddfsdemo.eco.cdb
........\..\ddfsdemo.eds_overflow
........\..\ddfsdemo.fit.qmsg
........\..\ddfsdemo.hier_info
........\..\ddfsdemo.hif
........\..\ddfsdemo.map.bpm
........\..\ddfsdemo.map.cdb
........\..\ddfsdemo.map.ecobp
........\..\ddfsdemo.map.hdb
........\..\ddfsdemo.map.logdb
........\..\ddfsdemo.map.qmsg
........\..\ddfsdemo.map_bb.cdb
........\..\ddfsdemo.map_bb.hdb
........\..\ddfsdemo.map_bb.logdb
........\..\ddfsdemo.pre_map.cdb
........\..\ddfsdemo.pre_map.hdb
........\..\ddfsdemo.psp
........\..\ddfsdemo.pss
........\..\ddfsdemo.rpp.qmsg
........\..\ddfsdemo.rtlv.hdb
........\..\ddfsdemo.rtlv_sg.cdb
........\..\ddfsdemo.rtlv_sg_swap.cdb
........\..\ddfsdemo.sgate.rvd
........\..\ddfsdemo.sgate_sm.rvd
........\..\ddfsdemo.sgdiff.cdb
........\..\ddfsdemo.sgdiff.hdb
........\..\ddfsdemo.signalprobe.cdb
........\..\ddfsdemo.sim.cvwf
........\..\ddfsdemo.sim.hdb
........\..\ddfsdemo.sim.qmsg
........\..\ddfsdemo.sim.rdb
........\..\ddfsdemo.sld_design_entry.sci
........\..\ddfsdemo.sld_design_entry_dsc.sci
........\..\ddfsdemo.syn_hier_info
........\..\ddfsdemo.tan.qmsg
........\..\prev_cmp_ddfsdemo.asm.qmsg
........\..\prev_cmp_ddfsdemo.fit.qmsg
........\..\prev_cmp_ddfsdemo.map.qmsg
........\..\prev_cmp_ddfsdemo.sim.qmsg
........\..\prev_cmp_ddfsdemo.tan.qmsg
........\..\wed.wsf
........\DDFSCore.bsf
........\DDFSCore.vhd
........\ddfsdemo.asm.rpt
........\ddfsdemo.bdf
........\ddfsdemo.done
........\ddfsdemo.dpf
........\ddfsdemo.fit.rpt
........\ddfsdemo.fit.smsg
........\ddfsdemo.fit.summary
........\ddfsdemo.flow.rpt
........\ddfsdemo.map.rpt
........\ddfsdemo.map.summary
........\ddfsdemo.pin
........\ddfsdemo.pof
........\ddfsdemo.qpf
........\ddfsdemo.qsf
........\ddfsdemo.qws
........\ddfsdemo.sim.rpt
........\ddfsdemo.sof
........\ddfsdemo.tan.rpt
........\ddfsdemo.tan.summary
........\DualPortRam.bsf
........\DualPortRam.cmp
........\DualPortRam.vhd
........\DualPortRam_waveforms.html
........\greybox_tmp
........\MCUInterFace.bsf
........\MCUInterface.vhd
........\pll.bsf
........\pll.cmp
........\pll.ppf
........\pll.vhd
........\pll_waveforms.html
........\prev_cmp_ddfsdemo.qmsg
........\sin_ram2_1024.mif
Download