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[Other resource] ddfs

Description: 我自己用vhdl实现编的dds，能实现正弦波，方波，三角波。-my own use VHDL to achieve series dds, able sine, square, triangle wave.
Platform: | Size: 87754 | Author: 黎明 | Hits:

[Other resource] DDFS_1

Description: 主要介绍DDFS的主要结构，和它的实现方法还有源代码（VHDL）-introduces the main structure and the implementation methods have the source code (VHDL)
Platform: | Size: 3165 | Author: 李逵 | Hits:

[File Operate] jiyufpgadds

Description: 直接数字频率合成（Direct Digital Fraquency Synthesis,即DDFS，一般简称DDS）是从相位概念出发直接合成所需要波形的一种新的频率合成技术。
Platform: | Size: 101281 | Author: 王永 | Hits:

[VHDL-FPGA-Verilog] ddfs

Description: 我自己用vhdl实现编的dds，能实现正弦波，方波，三角波。-my own use VHDL to achieve series dds, able sine, square, triangle wave.
Platform: | Size: 87040 | Author: 黎明 | Hits:

[Data structs] DDFS_1

Description: 主要介绍DDFS的主要结构，和它的实现方法还有源代码（VHDL）-introduces the main structure and the implementation methods have the source code (VHDL)
Platform: | Size: 3072 | Author: 李逵 | Hits:

[Documents] SOPCofDDS

Description: 基于SOPC的DDS信号源的实现，文章不错，值得借鉴。-based SOPC DDS signal source and that the realization of the article is true, which is worth learning from.
Platform: | Size: 147456 | Author: 高超 | Hits:

Description: 文中给出了用VHDL实现三角波正弦波方波的代码, 可以在maxPLUX2上运行,-In this paper, using the VHDL-wave sine wave square wave triangle realize the code, you can run maxPLUX2,
Platform: | Size: 2048 | Author: qibinchuan | Hits:

[File Format] jiyufpgadds

Description: 直接数字频率合成（Direct Digital Fraquency Synthesis,即DDFS，一般简称DDS）是从相位概念出发直接合成所需要波形的一种新的频率合成技术。-Direct Digital Synthesis (Direct Digital Fraquency Synthesis, that is, DDFS, generally referred to as DDS) is a departure from the concept phase direct synthesis of waveforms needed for a new frequency synthesis.
Platform: | Size: 101376 | Author: 王永 | Hits:

[VHDL-FPGA-Verilog] FPGAddfs

Description: 基于FPGA的直接数字频率合成器的设计与实现.-FPGA-Based Direct Digital Frequency Synthesizer Design and Implementation.
Platform: | Size: 222208 | Author: 周真 | Hits:

[Software Engineering] pllddfs

Description: 一种基于锁相环的数字频率合成器的设计-Based on Phase-Locked Loop Digital Frequency Synthesizer Design
Platform: | Size: 111616 | Author: 周真 | Hits:

[VHDL-FPGA-Verilog] vhdlddfs

Description: 用VHDL设计直接数字频率合成器-VHDL design with direct digital frequency synthesizer
Platform: | Size: 190464 | Author: 周真 | Hits:

[VHDL-FPGA-Verilog] ddfs

Description: 使用单片机控制FPGA完成直接数字频率合成(DDFS),采用Keil C51-Complete single-chip FPGA to control the use of direct digital frequency synthesizer (DDFS), using Keil C51
Platform: | Size: 62464 | Author: 失落 | Hits:

[Data structs] DDFS

Description: ddfs 频率合成技术的课件东南大学经典课件讲的很详细-failed to translate
Platform: | Size: 395264 | Author: li | Hits:

[Other] e

Description: 《EDA技术实用教程》实验选编专题一：计数分频器设计 4 专题二：存储器定制 7 实验一：快速乘法器电路设计 11 实验二：高速数字相关器设计 17 实验三：TLC5510高速A/D转换器控制 21 实验四：直接数字频率合成器（DDFS）设计 23 实验五：基于直接数字频率合成技术的任意波形发生器-" EDA technology practical course" Selected experimental one topic: the design count crossovers feature 4 2: 7 experiment a custom memory: Fast multiplier circuit design of 11 experiments II: the design of high-speed digital correlator 17, the experiment three: TLC5510 high-speed A/D converter control 21 of the experiment four: Direct Digital Frequency Synthesizer (DDFS) experimental design, 23 5: Based on Direct Digital Synthesis technology, arbitrary waveform generator
Platform: | Size: 2693120 | Author: 耿守浩 | Hits:

[VHDL-FPGA-Verilog] ddfs

Description: 基本FPGA的DDS信号发生器，可产生1-1MHZ任意频率的三角波，方波，锯齿波，正弦波-Basic FPGA-DDS signal generator, can produce 1-1MHZ arbitrary frequency triangle wave, square wave, sawtooth, sine wave
Platform: | Size: 1373184 | Author: 吴宏伟 | Hits:

[VHDL-FPGA-Verilog] ddfsdemo

Description: 直接数字频率合成器（Direct Digital Frequency Synthesizer：DDFS）的VHDL程序,开发环境是QuartusII,系统时钟为50MHz，由PLL产生DDFS的工作时钟166.67MHz,地址位宽为24位，频率字为20，相位字为10，RAM用于存储查找表，其地址位宽为10，数据位宽为8。-Direct Digital Frequency Synthesizer ( DDFS) of the VHDL program, the development environment is QuartusII, the system clock to 50MHz, the work of DDFS generated by PLL clock 166.67MHz, address bit-width of 24-bit frequency word is 20, phase word for 10, RAM used to store look-up table, its address is 10 bits wide, the data is 8 bits wide.
Platform: | Size: 647168 | Author: 力文 | Hits:

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[Other resource] ddfs

[Other resource] DDFS_1

[File Operate] jiyufpgadds

[VHDL-FPGA-Verilog] ddfs

[Data structs] DDFS_1

[Documents] SOPCofDDS

[VHDL-FPGA-Verilog] DDS234

[File Format] jiyufpgadds

[VHDL-FPGA-Verilog] FPGAddfs

[Software Engineering] pllddfs

[VHDL-FPGA-Verilog] vhdlddfs

[VHDL-FPGA-Verilog] ddfs

[Data structs] DDFS

[Other] e

[VHDL-FPGA-Verilog] ddfs

[VHDL-FPGA-Verilog] ddfsdemo

[VHDL-FPGA-Verilog] ddfs

[Mathimatics-Numerical algorithms] DDFS

[VHDL-FPGA-Verilog] DDFS

[Documents] ddfs-sample-code

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