Search - E1 vhdl

[VHDL-FPGA-Verilog] Y312448

Description: 基于VHDL的SDH专用芯片的TOP-DOWN设计，内有全套源码以及图片，内容详尽，绝对真实可靠！-VHDL based on the SDH ASIC Design TOP-DOWN, which has a full set of source code, as well as pictures, and detailed, reliable and absolutely true!
Platform: | Size: 2607104 | Author: 殷彦伟 | Hits:

[Windows Develop] sdh

Description: SDH是现代光纤通信中广泛应用的数据传输格式,在SDH帧结构中，前9列为开销字节，它包含了很多重要的信息，本程序为SDH开销的接收处理，查找帧头，分频，勤务话字节E1异步fifo。可拆为三段源代码，不知道能不能抵三个程序-SDH is a modern optical fiber communication is widely used in data transmission format, in the SDH frame structure, as the former 9 overhead bytes, it contains a lot of important information, the procedures for receiving SDH overhead processing, search header, sub-frequency ,勤務if E1 asynchronous byte fifo. Removable for three source code, I do not know the three procedures can be arrived
Platform: | Size: 6144 | Author: 韩冰 | Hits:

[VHDL-FPGA-Verilog] 32ET_source

Description: 32时隙的VHDL源代码在开发E1 2M线路的时候非常有用-32 slot of the VHDL source code in the development of E1 2M lines is very useful when
Platform: | Size: 1024 | Author: 王鹏 | Hits:

[VHDL-FPGA-Verilog] SDHAnalysis

Description: 光纤通信中的SDH数据帧解析及提取的VHDL实现源代码，共包含帧同步、E1及F1码流提取、DCC1码流提取、帧头开销串行输出四个主要模块-SDH fiber-optic communication data frame analysis and retrieval implementation of VHDL source code, include the frame synchronization, E1 and F1 stream extraction, DCC1 stream extraction, header overhead serial output four main modules
Platform: | Size: 31744 | Author: 张晓彬 | Hits:

[VHDL-FPGA-Verilog] vhdlcode1

Description: E1 (FIRST ORDER EUROPE TRANSMISSION STANDARD)vhdl
Platform: | Size: 5120 | Author: padavala gangadhar | Hits:

[VHDL-FPGA-Verilog] shift

Description: E1接收部分主要功能是实现从输入的差分线路数据中恢复出2.048M线路时钟并将数据解码输出。包括解码和线路时钟恢复两模块。-E1 to receive some of the major functions of the difference from the input data lines to recover a clock and data lines 2.048M decoder output. Including decoding and clock recovery circuits of two modules.
Platform: | Size: 89088 | Author: liusen | Hits:

[Other] E1-FramerDeframer

Description: E1 Framer/Deframer,E1 framer Deframer core implements CCITT (ITU) recommedations G.704,G.706 and G.732 for 30 channel multiplexed E1 stream at 2.048Mbps rate. Note:This project is part of the OpenStacks initiative at the Telecom Software Laboratory, Electrical Engineering Department / Bharti School of Telecommunication Technology & Management. The initiative is founded and led by Dr.Subrat Kar (subrat@ee.iitd.ac.in) at the Department of Electrical Engineering, IIT Delhi-E1 Framer/Deframer, E1 framer Deframer core implements CCITT (ITU) recommedations G.704, G.706 and G.732 for 30 channel multiplexed E1 stream at 2.048Mbps rate. Note: This project is part of the OpenStacks initiative at the Telecom Software Laboratory, Electrical Engineering Department/Bharti School of Telecommunication Technology & Management. The initiative is founded and led by Dr.Subrat Kar (subrat@ee.iitd.ac.in) at the Department of Electrical Engineering, IIT Delhi
Platform: | Size: 139264 | Author: xiao | Hits:

[VHDL-FPGA-Verilog] E1framerDeframer

Description: e1 framer and defremerr vhdl cods
Platform: | Size: 45056 | Author: rez | Hits:

[VHDL-FPGA-Verilog] E1

Description: 在国际标准组织开放式系统互联（OSI）参考模型下，以太网是第二层协议。10G以太网使用ＩＥＥＥ（电气与电子工程师学会）802.3以太网介质访问控制协议（ＭＡＣ）、ＩＥＥＥ 802.3以太网帧格式以及ＩＥＥＥ 802.3最小和最大帧尺寸。-In the International Standards Organization Open Systems Interconnect (OSI) reference model, Ethernet is the second-layer protocol. 10G Ethernet using the IEEE (Institute of Electrical and Electronics Engineers) 802.3 Ethernet Media Access Control Protocol (MAC), IEEE 802.3 Ethernet frame format, as well as the minimum and maximum IEEE 802.3 frame size.
Platform: | Size: 1723392 | Author: guoguo | Hits:

[Modem program] MuxDemux_E1_E3

Description: Multiplexer and demultiplexer from E1 to E3 stream
Platform: | Size: 6144 | Author: sai | Hits:

[VHDL-FPGA-Verilog] HDLC_E1

Description: E1到HDLC转换实现E1到以太网 E1到HDLC转换实现E1到以太网-E1 TO HDLC E1 TO ETHETH
Platform: | Size: 449536 | Author: robincyh | Hits:

[VHDL-FPGA-Verilog] led_control

Description: 本实验箱采用的液晶显示屏内置的控制器为SED1520，点阵为122×32，需要两片SED1520组成，由E1，E2分别选通，以控制显示屏的左右两半屏。图形液晶显示模块有两种连接方式，一种为直接访问方式，一种为间接访问方式。本实验采用直接控制方式。直接控制方式就是将液晶显示模块的接口作为存储器或I/O设备直接挂在计算机总线上。计算机通过地址译码器控制E1和E2的选通；读/写操作信号R/W有地址线A1 控制，命令/数据寄存器选择信号由地址线A0控制。 -The experimental box with built-in LCD controller for the SED1520, lattice is 122 × 32, needs two SED1520 formed by the E1, E2, respectively gating to control the display of about two and a half screen. Graphic LCD module has two connections, one for the direct access method, an indirect access. In this study the direct control mode. Direct control method is to interface LCD module as memory or I/O devices directly linked to the computer bus. Computer controlled by address decoder strobe E1 and E2 read/write signal R/W control the address lines A1, command/data register select control signal from the address line A0.
Platform: | Size: 1206272 | Author: yangxiao | Hits:

[Post-TeleCom sofeware systems] E1_to_e3_v.2.1

Description: E1信号到E3复用解复用VHDL代码包括时钟合成-E1 to E3 multiplexing & demultiplexing VHDL code, ，including clock synthesis
Platform: | Size: 16321536 | Author: john | Hits:

[Communication-Mobile] muxdemux_4E1(E2)_to_1E2(E3)

Description: framer Deframer core multiplexed 4 E1(E2)channel s to one E2(E3) stream at 8.448Mbps(34.368Mbps) rate .
Platform: | Size: 3072 | Author: Oleg | Hits:

[VHDL-FPGA-Verilog] MuxDemux_E1_E3

Description: E3 -Mux / Demux - Multiplexer of 16 E1 Channels-E3 -Mux / Demux - Multiplexer of 16 E1 Channels
Platform: | Size: 7168 | Author: qi | Hits:

[VHDL-FPGA-Verilog] e1_vhdl

Description: 用VHDL在FPGA内部实现E1的接口，适合通讯相关专业硬件开发使用-Within the FPGA implementation using VHDL E1 interface, the hardware for communications-related professional development to use
Platform: | Size: 18432 | Author: 彭涛 | Hits:

[VHDL-FPGA-Verilog] E1

Description: 分析帧同步算法，提供帧同步的状态机实现图以及得到的正确仿真图形。-Analysis of frame synchronization algorithm, to provide frame synchronization state machine implementation plans and get the correct simulation graphics.
Platform: | Size: 96256 | Author: 李逊 | Hits:

[VHDL-FPGA-Verilog] PCK_CRC4_D4

Description: E1成帧模块，使用VHDL语言设计中的CRC4校验码生成模块-E1 framing module, using the VHDL language design CRC4 check code generation module
Platform: | Size: 1024 | Author: | Hits:

[Other] mux-e1-e2--vhdl-elastic-buffer

Description: this is a good vhdl elastic buffer
Platform: | Size: 3761152 | Author: has | Hits:

[VHDL-FPGA-Verilog] e1framerdeframer_latest.tar

Description: e1 framder deframer.
Platform: | Size: 17408 | Author: aprsc7 | Hits:

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[VHDL-FPGA-Verilog] Y312448

[Windows Develop] sdh

[VHDL-FPGA-Verilog] 32ET_source

[VHDL-FPGA-Verilog] SDHAnalysis

[VHDL-FPGA-Verilog] vhdlcode1

[VHDL-FPGA-Verilog] shift

[Other] E1-FramerDeframer

[VHDL-FPGA-Verilog] E1framerDeframer

[VHDL-FPGA-Verilog] E1

[Modem program] MuxDemux_E1_E3

[VHDL-FPGA-Verilog] HDLC_E1

[VHDL-FPGA-Verilog] led_control

[Post-TeleCom sofeware systems] E1_to_e3_v.2.1

[Communication-Mobile] muxdemux_4E1(E2)_to_1E2(E3)

[VHDL-FPGA-Verilog] MuxDemux_E1_E3

[VHDL-FPGA-Verilog] e1_vhdl

[VHDL-FPGA-Verilog] E1

[VHDL-FPGA-Verilog] PCK_CRC4_D4

[Other] mux-e1-e2--vhdl-elastic-buffer

[VHDL-FPGA-Verilog] e1framerdeframer_latest.tar

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