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[VHDL-FPGA-Verilog] source_files

Description: FPGA与DSP的EMIFA口接口程序.在FPGA内分配了两块双BUFFER与DSP进行通信.-FPGA and DSP EMIFA mouth interface program. The FPGA distribution within the two-SUBJECT ER and DSP communication.
Platform: | Size: 7168 | Author: tanbo | Hits:

[VHDL-FPGA-Verilog] DSP_EMIF_if

Description: fpga开发的程序，内容都不错，主要是top_test-FPGA development process, the contents are good, mainly top_test
Platform: | Size: 1024 | Author: bob | Hits:

[VHDL-FPGA-Verilog] FIFO_EMIF

Description: 实现FPGA通过EMIF总线给DSP定期发送数据的功能-FPGA implementation through the EMIF bus regularly send data to the DSP function
Platform: | Size: 1480704 | Author: 徐成发 | Hits:

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