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[Embeded-SCM Develop] da

Description: 设计一个简单的LED流水彩灯,12个彩灯共阴接地,阳极分别与EP1C3的8个I/O相连,来控制彩灯的灭亮,在不同时段,指示灯有不同的显示模式.
Platform: | Size: 923 | Author: chenli | Hits:

[Other resource] cunshiboqi

Description: 采用高速AD的存储示波器设计，基于EP1C3板GWADDA板存储示波器，内有说明文件
Platform: | Size: 1055054 | Author: 姚大雷 | Hits:

[Embeded-SCM Develop] Mars-EP1C3-S核心板源码和原理图

Description: FPGA Mars-EP1C3-S核心板源码和原理图
Platform: | Size: 10184447 | Author: xiaopi_xqb@sina.com | Hits:

[VHDL-FPGA-Verilog] cunshiboqi

Description: 采用高速AD的存储示波器设计，基于EP1C3板GWADDA板存储示波器，内有说明文件-AD using high-speed storage oscilloscope design, based on EP1C3 board GWADDA board storage oscilloscope, which has the documentation
Platform: | Size: 1054720 | Author: 姚大雷 | Hits:

[SCM] fpga_drive_ad7892

Description: 利用FPGA驱动12位的AD7892进行模数变换，并将数据存储到SRAM中。FPGA型号为EP1C3-144。并通过LED将12位AD值显示出来。-The use of FPGA-driven 12-bit AD7892 analog to digital conversion, and data is stored in the SRAM. FPGA model EP1C3-144. Through the LED will be 12-bit AD value is displayed.
Platform: | Size: 504832 | Author: shuaige | Hits:

[Software Engineering] FPGA_ep1c3-144-core

Description: 用PROTEL软件设计的FPGA最小系统板。FPGA的型号为EP1C3-144，需要制作最小系统板的可以参考一下。-PROTEL software design of the FPGA with the minimum system board. FPGA-model EP1C3-144, need to make the minimum system board that can be reference.
Platform: | Size: 162816 | Author: shuaige | Hits:

[Documents] 11912911lunwen

Description: 本文主要介绍以EP1C3/EP1C6芯片进行十字路口的交通控制灯的设计，该系统可控制2个方向的红、黄、绿三盏灯,让其按特定的规律进行变化。用EP1C3/EP1C6作为交通控制灯的主控芯片，采用VHDL语言编写控制程序，利用MAX+PlusⅡ对设计结果进行仿真，发现系统工作性能良好。据此设计而成的硬件电路,也实现了控制要求。该设计展示了VHDL语言的强大功能和优秀特性。-This paper introduces the crossroads EP1C3/EP1C6 chip design of traffic control lights, the system can control the direction of two red, yellow, green, three lights, let the law be changed according to the specific. As a traffic control light with EP1C3/EP1C6 master chip, using VHDL language control program, using MAX+ Plus Ⅱ design simulation results and found that system works good performance. Accordingly designed with the hardware circuit, also achieved control requirements. The design shows the power of VHDL language and excellent features.
Platform: | Size: 300032 | Author: 灰太狼 | Hits:

[VHDL-FPGA-Verilog] EP1C3

Description: fpga LCD 最小系统开发板原理图还内存与SRAM-fpga LCD development board schematics minimum system memory and SRAM is also
Platform: | Size: 139264 | Author: bisedeng | Hits:

[VHDL-FPGA-Verilog] interface

Description: 采用Cyclone EP1C3，VHDL程序算法实现了信号波形的实时采样并回放，同时能测量时域信号的频率，通过与MCU的8位并行接口，进行相互通信。-Using Cyclone EP1C3, VHDL program algorithm of the signal waveform of real-time sampling and playback at the same time capable of measuring the frequency of the signal in time domain, through a MCU 8-bit parallel interface to communicate with each other.
Platform: | Size: 4750336 | Author: 姚益武 | Hits:

[VHDL-FPGA-Verilog] EP1C3

Description: schematic altera EP1C12
Platform: | Size: 62464 | Author: Marcos Vin铆cius | Hits:

[VHDL-FPGA-Verilog] EP1C3

Description: 这是一个用Verilog语言编写的一组程序，主要是熟悉开发板的应用，以及verilog语言-This is a Verilog language with a set of procedures, mainly familiar with the application development board, and the verilog language
Platform: | Size: 16773120 | Author: wanglixia | Hits:

[VHDL-FPGA-Verilog] ep1c3

Description: 里面有最基本的FPGA的开发板的所有例子，很多都是相当的经典-There are basic FPGA development board for all the examples, many of which are fairly classic
Platform: | Size: 3540992 | Author: luogui | Hits:

[Embeded-SCM Develop] Ep1c_3logic_analysis

Description: 使用ALTERA EP1C3器件DIY逻辑分析仪逻辑分析仪是一种类似于示波器的波形测试设备，它可以监测硬件电路工作时的逻辑电平（高或低），存储后用图形的方式直观地表达出来，主要是方便用户在数字电路的调试中观察输出的逻辑电平值。-DIY devices using ALTERA EP1C3 logic analyzer logic analyzer is an oscilloscope waveform similar test equipment, which can monitor the hardware circuit when the logic level (high or low), stored for later use intuitive graphical way to express, mainly to facilitate the user to debug digital circuits observed in the output logic level value.
Platform: | Size: 3596288 | Author: MRIKO | Hits:

[VHDL-FPGA-Verilog] ep1c3_sd_vga_photo

Description: 使用EP1C3器件DIY 数码相框之所以选择 DIY 数码相框，并不是期望可以做个多么像样的产品出来，毕竟消费类数码产品的市场竞争是很激烈的，任何一个成熟产品的成本都会被剥削到最低。市场上的数码相框一般是以带液晶驱动外设的 ARM 处理器为主实现上述的所有功能，而这个工程恰恰相反，所有的功能也都会使用 FPGA 来完成。但是话说回来，FPGA 是硬件，虽然有很多硬件固有特性所具备的优势，但是其设计灵活性方面还是和软件无法媲美的，所以这个工程项目最终实现的数码相框的功能会打一些折扣。-DIY Digital Photo Frame with EP1C3 device DIY digital photo frame chosen, do not expect to be a decent product out how, after all, digital consumer products Market competition is very fierce, the cost of any mature products will be exploited to a minimum. A digital photo frame on the market LCD driver as is with ARM processor-based peripherals to achieve all of the features mentioned above, and this project on the contrary, all The feature also will use the FPGA to complete. But then again, FPGA hardware, although there are many inherent characteristics of the hardware Have the advantage, but its design flexibility and software is still not comparable, so the eventual realization of this project Digital Photo Frame features will play some discounts.
Platform: | Size: 10691584 | Author: MRIKO | Hits:

[VHDL-FPGA-Verilog] LCD1602_LEVEL4

Description: 基于FPGA-EP1C3的LCD1602驱动程序。模块化-Based on FPGA-EP1C3 the LCD1602 driver. Modular
Platform: | Size: 573440 | Author: 轩辕镜月 | Hits:

[VHDL-FPGA-Verilog] FPGA_ep1c3

Description: ALTERA EP1C3 PROTEL 原理图与PCB-ALTERA EP1C3 PROTEL SCH AND PCB
Platform: | Size: 163840 | Author: | Hits:

[VHDL-FPGA-Verilog] fifo_ex4

Description: 深入浅出玩转FPGA代码实验四FIFO模块基于EP1C3-Layman Fun FPGA code EP1C3 based experimental four FIFO modules
Platform: | Size: 256000 | Author: 王新 | Hits:

[VHDL-FPGA-Verilog] EP1C3-board

Description: 基于EP1C3的进阶实验——配套书中笔记17的大量实验代码工程。-The EP1C3-based advanced experiments- supporting the book notes 17 experimental code works.
Platform: | Size: 16887808 | Author: gcy | Hits:

[Other] EP1C3

Description: 基于EP1C3的进阶实验——配套书中笔记17的大量实验代码工程。 -Based on EP1C3 of form a complete set of advanced experiment- the book notes 17 large trials of the code project.
Platform: | Size: 16613376 | Author: mr.xiang | Hits:

[VHDL-FPGA-Verilog] EP1C3-uart_1_verilog

Description: EP1C3-uart_1_verilog,程序实现了一个收发一帧10个bit（即无奇偶校验位）的串口控制器，10个bit是1位起始位，8个数据位，1个结束位。串口的波特律由程序中定义的div_par参数决定，更改该参数可以实现相应的波特率。程序当前设定的div_par 的值是0x145，对应的波特率是9600。用一个8倍波特率的时钟将发送或接受每一位bit的周期时间划分为8个时隙以使通信同步.-EP1C3-uart 1 verilog, implements a program to send and receive a 10 bit (that is, no parity bit) serial controller, 10 bit is a start bit, 8 data bits, 1 stop bit. Baud-law decided by div_par parameters defined in the program, you can change the parameters to achieve the appropriate baud rate. Value of the program is currently set div_par Is 0x145, the corresponding baud rate is 9600. An 8 times the baud rate clock to send or receive every bit of the time period is divided into eight time slots so that the pass Letter synchronization.
Platform: | Size: 342016 | Author: davidobt | Hits:

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[Embeded-SCM Develop] da

[Other resource] cunshiboqi

[Embeded-SCM Develop] Mars-EP1C3-S核心板源码和原理图

[VHDL-FPGA-Verilog] cunshiboqi

[SCM] fpga_drive_ad7892

[Software Engineering] FPGA_ep1c3-144-core

[Documents] 11912911lunwen

[VHDL-FPGA-Verilog] EP1C3

[VHDL-FPGA-Verilog] interface

[VHDL-FPGA-Verilog] EP1C3

[VHDL-FPGA-Verilog] EP1C3

[VHDL-FPGA-Verilog] ep1c3

[Embeded-SCM Develop] Ep1c_3logic_analysis

[VHDL-FPGA-Verilog] ep1c3_sd_vga_photo

[VHDL-FPGA-Verilog] LCD1602_LEVEL4

[VHDL-FPGA-Verilog] FPGA_ep1c3

[VHDL-FPGA-Verilog] fifo_ex4

[VHDL-FPGA-Verilog] EP1C3-board

[Other] EP1C3

[VHDL-FPGA-Verilog] EP1C3-uart_1_verilog

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