Search - EP1C6Q240C8

[Other resource] SmartSOPC_Board_Cyclone_1C6

Description: sopc开发板标准NIOSII模块，用于EP1C6Q240C8芯片（FPGA）
Platform: | Size: 645466 | Author: 石林 | Hits:

[Other] lcd

Description: EP1C6Q240C8的examples lcd测试程序
Platform: | Size: 1331 | Author: shang | Hits:

[Other] FLASH_DEMO

Description: EP1C6Q240C8的examples flash测试程序
Platform: | Size: 342873 | Author: shang | Hits:

[Other] mouse_demo

Description: EP1C6Q240C8的examples 鼠标口测试程序
Platform: | Size: 58080 | Author: shang | Hits:

Description: 摘要：直接数字频率合成(DDS)是七十年代初提出的一种新的频率合技术，其数字结构满足了现代电子系统的许多要求，因而得到了迅速地发展。现场可编程门阵列器件(FPGA)的出现，改变了现代电子数字系统的设计方法，提出了一种全新的设计模式。本设计结合这两项技术，并利用单片机控制灵活的特点，开发了一种新的函数波形发生器。在实现过程中，本设计选用了Altera公司的EP1C6Q240C8芯片作为产生波形数据的主芯片，充分利用了该芯片的超大集成性和快速性。在控制芯片上选用了AT89C51单片机作为控制芯片。本设计中，FPGA芯片的设计和与控制芯片的接口设计是一个难点，本文利用Altera的设计工具Quartus II并结合Verilog-HDL语言，采用硬件编程的方法很好地解决了这一问题。本文首先介绍了函数波形发生器的研究背景和DDS的理论。然后详尽地叙述了用EP1C6Q240C8完成DDS模块的设计过程，这是本设计的基础。接着分析了整个设计中应处理的问题，根据设计原理就功能上进行了划分，将整个仪器功能划分为控制模块、外围硬件、FPGA器件三个部分来实现。然后就这三个部分分别详细地进行了阐述。最后，通过系列实验，详细地说明了本设计的功能、性能、实现和实验结果。并结合在设计中的一些心得体会，提出了本设计中的一些不足和改进意见。通过实验说明，本设计达到了预定的要求，并证明了采用软硬件结合，利用DDS技术实现函数波形发生器的方法是可行的。关键词：直接数字频率合成；现场可编程门阵列；函数波形发生器；频谱分析；仿真含图原版论文
Platform: | Size: 2195647 | Author: nacker@126.com | Hits:

[Software Engineering] SmartSOPC_Board_Cyclone_1C6

Description: sopc开发板标准NIOSII模块，用于EP1C6Q240C8芯片（FPGA）-SOPC development board NIOSII standard module for EP1C6Q240C8 chip (FPGA)
Platform: | Size: 645120 | Author: 石林 | Hits:

[Other] lcd

Description: EP1C6Q240C8的examples lcd测试程序-EP1C6Q240C8 the examples lcd test procedures
Platform: | Size: 1024 | Author: shang | Hits:

[Other] FLASH_DEMO

Description: EP1C6Q240C8的examples flash测试程序-EP1C6Q240C8 the examples flash test procedures
Platform: | Size: 343040 | Author: shang | Hits:

[Other] mouse_demo

Description: EP1C6Q240C8的examples 鼠标口测试程序-The examples I EP1C6Q240C8 mouse test procedures
Platform: | Size: 57344 | Author: shang | Hits:

[VHDL-FPGA-Verilog] key_matrix44

Description: FPGA EP1C6Q240C8 4*4键盘模块 4*4矩阵键盘，采用扫描方式检测按键-FPGA EP1C6Q240C8 4* 4 keyboard module 4* 4 matrix keyboard, using scanning detection button
Platform: | Size: 278528 | Author: lan | Hits:

[VHDL-FPGA-Verilog] 1602_jp

Description: FPGA lcd显示程序，可以扫描键盘输入，并在lcd上显示，-FPGA lcd display program, you can scan the keyboard input and display in lcd,
Platform: | Size: 478208 | Author: zdy | Hits:

[VHDL-FPGA-Verilog] FrequencySpectrum

Description: 基于ep1c6q240c8 fpga 及msp430fg4618混合控制器的频谱分析仪控制代码-Based on ep1c6q240c8 fpga and msp430fg4618 Hybrid Controller spectrum analyzer control code
Platform: | Size: 20133888 | Author: 张超 | Hits:

[VHDL-FPGA-Verilog] FullAdder

Description: 要求在Quartus II软件，利用VHDL完成层次式电路设计，电路中的元件可以用VHDL设计也可以用库元件连线构成再封装。借助EDA工具中的综合器，适配器，时序仿真器和编程器等工具进行相应处理。输入方法不限制。适配采用Cyclone系列的EP1C6Q240C8。要求综合出RTL电路，并进行仿真输入波形设计并分析电路输出波形。要求采用层次式结构设计。-Quartus II software requires the use of VHDL complete hierarchical circuit design, circuit components can also be used with VHDL design library components constitute a re-package connection. With a comprehensive EDA tool, adapter, timing emulator and programming tools such as dealt with accordingly. Input method is not restricted. Adaptation by Cyclone series EP1C6Q240C8. Required to synthesize the RTL circuit, and simulated input waveform design and analysis of the circuit output waveform. Requires a hierarchical structure design.
Platform: | Size: 1024 | Author: John | Hits:

[Windows Develop] NAT

Description: 乐器数字接口MIDI（Musical Instrument Digital Interface），是数字音乐的国际标准。任何电子乐器，只要能处理MIDI消息，并有合适的硬件接口，都可视为一个MIDI设备。本设计完成一个MIDI音乐播放器，该设备以MIDI技术为基础，在Altera公司Cyclone系列FPGA EP1C6Q240C8上实现数字音频合成。MIDI信号源由PC机串口配合串口MI-dssssdsfddsds
Platform: | Size: 182272 | Author: 杜永斐 | Hits:

[VHDL-FPGA-Verilog] vga

Description: 基于QuartusII 6.0 环境的vga驱动程序，所用芯片为EP1C6Q240C8,开发板时钟50M，显示模式800*600，72Hz，内容是在频幕显示几条直线。-Environment based on QuartusII 6.0 vga drivers, the chips for the EP1C6Q240C8, development board clock 50M, the display mode 800* 600,72 Hz, the frequency content of screen displays several lines.
Platform: | Size: 220160 | Author: x_metal | Hits:

[VHDL-FPGA-Verilog] keyboard4_4-and-seg7

Description: 4*4键盘扫描程序，并将键值利用七段数码管显示出来。芯片为Altera Cyclone EP1C6Q240C8。-It s very simple,for rookies.
Platform: | Size: 1024 | Author: 刘三虎 | Hits:

[VHDL-FPGA-Verilog] FPGA-based-multi-Divider

Description: 分频器是指使输出信号频率为输入信号频率1/N的电子电路,N是分频系数。在许多电子设备中如电子钟、频率合成器等，需要各种不同频率的信号协同工作，常用的方法是以稳定度高的晶体振荡器为主振源，通过变换得到所需要的各种频率成分，分频器是一种主要变换手段。本文当中，在分析研究和总结了分频技术的发展趋势的基础上，以实用、可靠、经济等设计原则为目标，介绍了基于FPGA的多种分频器的设计思路和实现方法。本设计采用EDA技术，以硬件描述语言VHDL为系统逻辑描述手段设计文件，在QuartusⅡ工具软件环境下，采用自顶向下的设计方法，由各个基本模块共同构建了一个基于FPGA的分频器。本次设计实现了包括整数、半整数和小数这三种不同类型分频器的分频，在设计过程中，系统主芯片采用EP1C6Q240C8，各个模块在QuartusⅡ上进行编程调试和仿真通过后，在GW48-SOPC上进行了下载。通过对各个部分测试后表明均能正确分频，完成了对系统的软件和硬件的设计，达到了系统的设计要求。 -Frequency divider refers to the frequency of the output signal as the input signal 1/N of electronic circuits. N is the frequency coefficient. In many electronic equipments such as the electronic clock, frequency synthesizers, which need different frequency signals work together and common way is to use the stability of the crystal oscillator as vibration source by converting the frequency components all needed. The frequency divider is a major means of conversion. In this paper, with the analytic study and review of trend basis of the technical frequency, a functional, reliable, economic and other design principles as the goal, this paper introduces a number of points frequency of the design and implementation based on FPGA. This design adopts the technology of EDA and hardware description language VHDL as logical description means of designing files. Under the environment of QuartusⅡ tools and the top-to-down approach, they build jointly a frequency divider by the basic modules base
Platform: | Size: 5120 | Author: 吴红梅 | Hits:

[VHDL-FPGA-Verilog] scan_led

Description: 每个时钟，计数时间，实现8的扫描显示，在数码管上依次显示13579bdf，可以选择EDA实验箱，FPGA EP1C6Q240C8。-Each clock, counting time, achieve 8 scan display, turn on the digital tube display 13579BDF, can choose EDA experimental box, FPGA EP1C6Q240C8.
Platform: | Size: 1024 | Author: LP | Hits:

[assembly language] 6c39b755f84775a3d8da072f766399e0

Description: 本文为数字时钟的设计介绍，具体说明如何使用QuartusⅡ软件设计一个基于EP1C6Q240C8芯片的数字钟。该数字钟具备以下功能：1.正常计时2.校正时间3.闹铃设置4.整点报时。-This paper describes the design of a digital clock, specifying how to use the software to design a QuartusⅡ EP1C6Q240C8 chips based on the digital clock. The digital clock has the following features: 1. normal time alarm setting 2. 3. 4. correction time hourly chime.
Platform: | Size: 150528 | Author: zw | Hits:

[VHDL-FPGA-Verilog] 1_2

Description: 基于cyclone EP1C6Q240C8的流水灯设计样本(a sample design of light water based on cyclone EP1C6Q240C8)
Platform: | Size: 404480 | Author: dark dragon | Hits:

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[Other resource] SmartSOPC_Board_Cyclone_1C6

[Other] lcd

[Other] FLASH_DEMO

[Other] mouse_demo

[SCM] 多功能高精度信号发生器的设计

[Software Engineering] SmartSOPC_Board_Cyclone_1C6

[Other] lcd

[Other] FLASH_DEMO

[Other] mouse_demo

[VHDL-FPGA-Verilog] key_matrix44

[VHDL-FPGA-Verilog] 1602_jp

[VHDL-FPGA-Verilog] FrequencySpectrum

[VHDL-FPGA-Verilog] FullAdder

[Windows Develop] NAT

[VHDL-FPGA-Verilog] vga

[VHDL-FPGA-Verilog] keyboard4_4-and-seg7

[VHDL-FPGA-Verilog] FPGA-based-multi-Divider

[VHDL-FPGA-Verilog] scan_led

[assembly language] 6c39b755f84775a3d8da072f766399e0

[VHDL-FPGA-Verilog] 1_2

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