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Description: 伪随机序列产生器－代进位反馈移位寄存器，verilog hdl 原代码。-Pseudo-random sequence generator- on behalf of binary feedback shift register, verilog hdl original code.
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Size: 1024 |
Author: 李辛 |
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Description: 伪随机序列产生器－代进位反馈移位寄存器，matlab 原代码。-Pseudo-random sequence generator- on behalf of binary feedback shift register, matlab source code.
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Size: 1024 |
Author: 李辛 |
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Description: 伪随机序列产生器，利用GOLLON 级联F-FCSR产生伪随机序列，FPGA实现功能，仿真，结果分析-Pseudo-random sequence generator using GOLLON cascade F-FCSR generate pseudo-random sequence, FPGA implementation function, simulation results analysis
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Size: 241664 |
Author: 李辛 |
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Description: 基于FPGA伪随机序列产生器，GOLLMANN级联F-FCSR，产生伪随机序列-FPGA-based pseudo-random sequence generator, GOLLMANN cascade F-FCSR, generating pseudo-random sequence
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Size: 2048 |
Author: 李辛 |
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Description: This paper addresses the usage of FCSR in place of LFSR in a stream cipher. To demonstrate the usage ZUC
stream cipher is taken as example in this paper. A good stream cipher should have good randomness, high
period, linear span, and security against any known attack. FCSR’s provide greater non-linearity than LFSR’s.
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Size: 152576 |
Author: ulvpshk |
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