Description: Pseudo-random sequence generator- on behalf of binary feedback shift register, verilog hdl original code.
- [turbo[1].Tar] - turbo code verilog procedures Interested
- [1] - Direct sequence spread spectrum PN code
- [rng] - random number generator to prepare Veril
- [ffcsr] - Pseudo-random sequence generator-filtere
- [prbs] - Pseudo-random number generator of the FP
- [DigitalEqualizer] - After the run of the MyEqualizer.m file
- [LTE] - simulink model for LTE link
- [viterbi] - Viterbi verilog generator
- [QIMO] - Verilog prepared arbitrary waveform gene
- [LFSR] - verilog to achieve 8-order pseudo-random
File list (Check if you may need any files):
fcsr.v
fcsr_test.v