Welcome！[Sign In] ！[Sign Up]！
Front-page it | Collect it | [中国-简体中文]
FAQ Fav
Location:
Search - FFT modelsim

Search list

[Other resource] fftmatlab

Description: fft在dspbuilder下产生VHDL源码及其测试激励文件的matlab模型,在modelsim下仿真通过-fft in dspbuilder under VHDL source code and test incentives document matl ab model, the simulation under through modelsim
Platform: | Size: 7812 | Author: zqh | Hits:

[Other resource] FFT_CORE

Description: FFT算法的VHDL语言实现 可在Modelsim上运行和调试 -FFT algorithm VHDL in the operation and Modelsim Debugging
Platform: | Size: 29769 | Author: 紫蓝 | Hits:

[Other] modelsim

Description: 基于存储器的基4按频率抽取的fft 的vhdl描述 可以对连续数据流进行256点的fft
Platform: | Size: 23146 | Author: 庞志勇 | Hits:

[VHDL-FPGA-Verilog] FFT_64point

Description: 该工程实现了一个64点DIF FFT，verilog编写，通过Modelsim功能仿真。
Platform: | Size: 16799 | Author: coolaler2010 | Hits:

[VHDL-FPGA-Verilog] 2Dfft

Description: VHDL 关于2DFFT设计程序 u scinode1 ∼ scinode9.vhd: Every SCI node RTL vhdl code. The details can be seen in the following section. u 2dfft.vhd: The top module includes these scinodes and form a 3x3 SCI Torus network, and it support these sub-modules scinode1∼ scinode9 reset and clk and global_cnt signals to synchronous the sub-modules to simplify the overall design. u proj2.wfc: VSS simulation result that is the same as the ModelSim simulation result. u Pro2_2.wfc: VSS simulation result of another test pattern can’t cause overflow situation.-VHDL design procedures on 2DFFT u scinode1
Platform: | Size: 783360 | Author: 李成 | Hits:

[VHDL-FPGA-Verilog] fftmatlab

Description: fft在dspbuilder下产生VHDL源码及其测试激励文件的matlab模型,在modelsim下仿真通过-fft in dspbuilder under VHDL source code and test incentives document matl ab model, the simulation under through modelsim
Platform: | Size: 7168 | Author: zqh | Hits:

[VHDL-FPGA-Verilog] FFT_CORE

Description: FFT算法的VHDL语言实现 可在Modelsim上运行和调试 -FFT algorithm VHDL in the operation and Modelsim Debugging
Platform: | Size: 29696 | Author: 紫蓝 | Hits:

[VHDL-FPGA-Verilog] modelsim

Description: 基于存储器的基4按频率抽取的fft 的vhdl描述 可以对连续数据流进行256点的fft -Memory based on the base 4 by the frequency of fft taken the VHDL description of the continuous data stream can be carried out 256 point fft
Platform: | Size: 22528 | Author: 庞志勇 | Hits:

[VHDL-FPGA-Verilog] CORDIC

Description: 介绍了CORDIC数字计算机的设计，采用的是verilogHDL,在modelsim上可以实现仿真验证，压缩包中包含CORDIC的工作结构图，比较详细-Introduced the CORDIC digital computer design, using the verilogHDL, can be achieved on the ModelSim simulation, compressed package that contains the work of CORDIC structure diagram, a more detailed
Platform: | Size: 141312 | Author: yaoyongshi | Hits:

[VHDL-FPGA-Verilog] Quartus_fft_ip_core

Description: Quartus中fft ip core的使用(modelsim 仿真FFT ip core 结合QUARTUS II 联合调试)-Fft ip core in Quartus use (modelsim simulation FFT ip core integration QUARTUS II Joint Commissioning)
Platform: | Size: 299008 | Author: 刘晓彬 | Hits:

[VHDL-FPGA-Verilog] FFT

Description: Verilog实现的FFT模块，供OFDM调制系统使用，可供大家参考学习-Verilog implementation FFT module for the OFDM modulation system used for your reference study
Platform: | Size: 1222656 | Author: 梁贵轩 | Hits:

[Algorithm] fft_model

Description: 基二的16点，每点16位FFT计算的modelsim完整工程，可以直接仿真运行-The base 2 of the 16 points, each 16-point FFT calculation modelsim full engineering, simulation can be directly run
Platform: | Size: 307200 | Author: 谈钒 | Hits:

[Crack Hack] 64R4SDFpoint_FFT

Description: 该工程实现了一个64点FFT，verilog编写，采用R4SDF结构，通过Modelsim功能仿真，压缩包里有rtl代码，dc脚本，输出报告。-The project implements a 64-point FFT, verilog compiled by R4SDF structure, through the Modelsim functional simulation, compression bag with rtl code, dc script, the output report.
Platform: | Size: 1255424 | Author: ShuChen | Hits:

[VHDL-FPGA-Verilog] 64pointFFTR2MDC

Description: 该工程实现了一个64点DIF FFT，verilog编写，采用R2MDC结构，通过Modelsim功能仿真，压缩包里有rtl代码，dc脚本，输出报告。-The project implements a 64-point DIF FFT, verilog compiled by R2MDC structure, through the Modelsim functional simulation, compression bag with rtl code, dc script, the output report.
Platform: | Size: 672768 | Author: ShuChen | Hits:

[VHDL-FPGA-Verilog] 32Kfft

Description: 32KFFT例程，适用于Quartus II 5.0 or later。- This design example requires the following software package: o Quartus II 5.0 or later o FFT MegaCore v2.1.3 o ModelSim version 6.0 or later
Platform: | Size: 998400 | Author: J | Hits:

[VHDL-FPGA-Verilog] FFT288

Description: 本部分是128点的fft,经过了modelsim的仿真验证.里面采用了华莱士树等结构,整体结构采用2-It is 128 point fft,which has been verificated in the modelsim.In the verilog code ,we use hulaishi tree.we use 288 architecture to complete it.
Platform: | Size: 1068032 | Author: gaod | Hits:

[VHDL-FPGA-Verilog] FFT_2c8

Description: 基于FPGA的fft，快速傅立叶变换，带仿真modelsim,硬件测试成功-FPGA-based fft, fast Fourier transform, with simulation modelsim, hardware test is successful
Platform: | Size: 13472768 | Author: 郑青松 | Hits:

[VHDL-FPGA-Verilog] FFT64DIF

Description: 实现64点的快速傅里叶运算，并用modelsim、matlab仿真。(Achieve fast Fourier operations at 64 points, and use Modelsim, matlab simulation.)
Platform: | Size: 20699136 | Author: chenmm | Hits:

[VHDL-FPGA-Verilog] exp_fft_test_724

Description: 在quartus软件中调用FFT的IP核，编辑IP核的驱动模块，使得IP核读入数据进行处理，输出数据。使用modelsim进行联合仿真。(In the quartus software, the IP kernel of FFT is called, and the driver module of the IP kernel is edited, so that the IP kernel is read into the data for processing and output data. Use Modelsim for joint simulation.)
Platform: | Size: 27558912 | Author: XHF72 | Hits:

[VHDL-FPGA-Verilog] fft_32k

Description: FFT 32K点设计实例v1.0.0自述文件 本自述文件包含以下部分： 工具要求 o Quartus II编译 o ModelSim仿真模型 o MATLAB模型(FFT 32K Point Design Example v1.0.0 README File This readme file for the Fast Fourier Transform (FFT) 32K Point Design contains information about the design example posted on the Altera Support website: http://www.altera.com/support/examples/exm-index.html Ensure that you have read the information on the design example web page before using the example. This readme file contains the following sections: o Package Contents o Tool Requirements o Quartus II Compilation o ModelSim Simulation Models o MATLAB Models o Core Directory Names o Release History o Design Examples Disclaimer o Contacting Altera)
Platform: | Size: 1120256 | Author: wsf-jv | Hits:
« 12 »

CodeBus www.codebus.net