Search - FIR FILTER-VERILOG CODE

[Other resource] two_d_fir

Description: FIR FILTER verilog code-FIR FILTER Verilog code
Platform: | Size: 26834 | Author: QQ | Hits:

[VHDL-FPGA-Verilog] FIR_1

Description: FIR滤波器的verilog实现，实现6级流水线的程序设计。-FIR filter Verilog, has implemented six lines of program design.
Platform: | Size: 1024 | Author: 李甫 | Hits:

[VHDL-FPGA-Verilog] two_d_fir

Description: FIR FILTER verilog code-FIR FILTER Verilog code
Platform: | Size: 26624 | Author: QQ | Hits:

[VHDL-FPGA-Verilog] fir_16

Description: fir滤波器-verilog，基于verilog的fir滤波器源码-fir filter-verilog, the fir filter based on the Verilog source code
Platform: | Size: 742400 | Author: zhc | Hits:

Description: 本文主要分析了FIR数字滤波器的基本结构和硬件构成特点,简要介绍了FIR滤波器实现的方式优缺点结合Altera公司的Stratix系列产品的特点,以一个基于MAC的8阶FIR数字滤波器的设计为例,给出了使用Verilog硬件描述语言进行数字逻辑设计的过程和方法,并且在QuartusⅡ的集成开发环境下编写HDL代码,进行综合利用QuartusⅡ内部的仿真器对设计做脉冲响应仿真和验证。-This paper analyzes the FIR digital filter structure and the basic hardware features, a brief introduction of the FIR filter the way to achieve the advantages and disadvantages of combining Altera s Stratix series of characteristics of the product, with a MAC based on the 8-order FIR digital filter design For example, given the use of Verilog hardware description language for digital logic design process and methods, and Quartus Ⅱ integrated development environment, prepared HDL code, for comprehensive utilization of Quartus Ⅱ emulator internal design so the impulse response simulation and verification.
Platform: | Size: 79872 | Author: sundan | Hits:

[VHDL-FPGA-Verilog] coeff_rom_0_7

Description: FIR filter basic verilog code for implementation-FIR filter basic verilog code for implementation
Platform: | Size: 2048 | Author: surya | Hits:

[VHDL-FPGA-Verilog] coeff_rom_1_6

Description: FIR filter basic verilog code for implementation-FIR filter basic verilog code for implementation
Platform: | Size: 2048 | Author: surya | Hits:

[VHDL-FPGA-Verilog] coeff_rom_2_5

Description: FIR filter basic verilog code for implementation-FIR filter basic verilog code for implementation
Platform: | Size: 2048 | Author: surya | Hits:

[VHDL-FPGA-Verilog] coeff_rom_3_4

Description: FIR filter basic verilog code for implementation-FIR filter basic verilog code for implementation
Platform: | Size: 2048 | Author: surya | Hits:

[VHDL-FPGA-Verilog] adder

Description: FIR filter basic verilog code for implementation-FIR filter basic verilog code for implementation
Platform: | Size: 1024 | Author: surya | Hits:

[VHDL-FPGA-Verilog] beta

Description: Fir verilog code implemented to find out the output of fir filter
Platform: | Size: 1024 | Author: dheeru | Hits:

[VHDL-FPGA-Verilog] fir_hdl

Description: 一个 FIR 滤波器的 verilog 实现，与 matlab 产生的 reference code 相互验证。-Verilog a FIR filter to achieve, with the reference code generated by matlab mutual authentication.
Platform: | Size: 97280 | Author: wei | Hits:

[VHDL-FPGA-Verilog] fir

Description: 数字电路设计中的，fir滤波器设计，我做的是8位宽的，利用vhdl实现，附带了完整的代码，报告，我没有对我的信息进行删除，是希望大家能够诚实的利用这个代码，提高自身本领。-Digital circuit design, fir filter design, I am doing is 8 bits wide, using vhdl implementation, with a complete code, the report, I did not delete my information in the hope that we can use this code for an honest to improve their skills.
Platform: | Size: 3322880 | Author: de de | Hits:

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[Other resource] two_d_fir

[VHDL-FPGA-Verilog] FIR_1

[VHDL-FPGA-Verilog] two_d_fir

[VHDL-FPGA-Verilog] fir_16

[Other] VerilogHDL

[VHDL-FPGA-Verilog] coeff_rom_0_7

[VHDL-FPGA-Verilog] coeff_rom_1_6

[VHDL-FPGA-Verilog] coeff_rom_2_5

[VHDL-FPGA-Verilog] coeff_rom_3_4

[VHDL-FPGA-Verilog] adder

[VHDL-FPGA-Verilog] beta

[VHDL-FPGA-Verilog] fir_hdl

[VHDL-FPGA-Verilog] fir

[Algorithm] fir_filter_verilog

[Software Engineering] FIR

[VHDL-FPGA-Verilog] fir_PGA

[VHDL-FPGA-Verilog] fir_filter_generator

[Editor] FIR-verilog

[Software Engineering] CODE-for-FIR-filter

[VHDL-FPGA-Verilog] dfe_filter

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