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[VHDL-FPGA-Verilog] DDS-320-modu

Description: 在采用 320x240 屏的设计实验箱上运行，产生正弦波，调幅调频波形，扫频。-320x240 screen using the design of experiments to run me generate sine wave, AM FM waveforms, sweep.
Platform: | Size: 1250304 | Author: hangyinli | Hits:

[Other] fulldigitalFMreceiver

Description: 这本书主要是讲，如何用VHDL语言来设计全数字FM接受机。（全英文）-This book mainly talk about how to design using VHDL language all-digital FM receivers. (Full English)
Platform: | Size: 658432 | Author: 廖大成 | Hits:

[Modem program] all_digital_fm_receiver_latest

Description: Fm receiver using DP-Fm receiver using DPLL
Platform: | Size: 112640 | Author: sai | Hits:

[VHDL-FPGA-Verilog] dds_final

Description: 使用Verilog HDL语言实现的一个DDS，可以发生0-10Mhz正弦波、方波、三角波，频率步进可调，FM调制、AM调制，调制度可调。DA芯片为8位并行，160MHz-Using the Verilog HDL language implementation of a DDS, can occur 0-10Mhz sine, square, triangle wave, frequency step tunable, FM modulation, AM modulation, adjustable modulation. DA-chip 8-bit parallel, 160MHz
Platform: | Size: 1638400 | Author: nostalgia | Hits:

[Algorithm] cordic_atan

Description: 用verilog语言实现计算反正切函数，在软件无线电中解调PM/FM中使用的尤为频繁。上传的压缩包是modelsim工程，基于6.5c,里边包含一个完整的PM波产生以及解调过程的matlab文件仿真，并取其中间的I和Q支路做为verilog文件的输入，并将其借条输出与MATLAB实际解调输出作比较。 鉴相器的设计基于CORDIC算法，其精度取决于迭代的深度。由于工程实际运用只需要解调出atan值，并不需要绝对的值，所以并没有给予加权，需要的同学可以自己加上。-Calculated using verilog language arc tangent function, the software radio demodulation PM/FM is particularly used frequently. From the archive is modelsim project, based on 6.5c, inside the PM contains a complete demodulation process of wave generation and simulation matlab file, and whichever is the middle of the I and Q branch verilog file as input, and its IOU demodulated output and actual output of MATLAB for comparison. Phase detector design is based on CORDIC algorithm, its accuracy depends on the iteration depth. As the practical application of engineering demodulated atan value only and does not need absolute value, and there is no weight given to the need of the students can add their own.
Platform: | Size: 79872 | Author: Jorge | Hits:

[VHDL-FPGA-Verilog] ep1c12_29_dds

Description: 基于周立功SOPC实验开发平台，利用VHDL语言，实现DDS调频-Zhou, who based SOPC experimental development platform, using VHDL language, to achieve DDS FM
Platform: | Size: 110592 | Author: Vincent Zhao | Hits:

[VHDL-FPGA-Verilog] all-digital-fm-receiver

Description: all digital fm receiver using vhdl programming language project for electronics and communication engineering students.
Platform: | Size: 1545216 | Author: Rahul | Hits:

[SCM] adfmreceiver

Description: The design of the All Digital FM Receiver circuit in this project uses Phase Locked Loop (PLL) as the main core. The task of the PLL is to maintain coherence between the input (modulated) signal frequency,iωand the respective output frequency,oωvia phase comparison. This self-correcting ability of the system also allows the PLL to track the frequency changes of the input signal once it is locked. Frequency modulated input signal is assumed as a series of numerical values (digital signal) via 8-bit of analog to digital conversion (ADC) circuit. The FM Receiver gets the 8 bit signal every clock cycle and outputs the demodulated signal. The All Digital FM Receiver circuit is designed using VHDL, then simulated and synthesized using ModelSim SE 6 simulator and Xilinx ISE 6.3i, respectively. FPGA implementation also provided, here we use Virtex2 device.
Platform: | Size: 658432 | Author: vijay | Hits:

[VHDL-FPGA-Verilog] simple_fm_receiver_latest.tar

Description: 用FPGA实现简单的FM接收机，d/a模块用扬声器-FPGA implementation using a simple FM receiver, d/a module with speaker
Platform: | Size: 1581056 | Author: 张昆 | Hits:

[VHDL-FPGA-Verilog] DigitalFM

Description: 用VHDL编写的一个全数字FM调谐接收机的源代码和详细资料，原文是英文，已经翻译成中文。 -One using VHDL digital FM tuner receiver source code and detailed information, the original is in English, has been translated into Chinese.
Platform: | Size: 1453056 | Author: xuegamgma | Hits:

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