Search - FPGA，DDS

[VHDL-FPGA-Verilog] 基于FPGA的数字频率计

Description: 基于FPGA的数字频率计
Platform: | Size: 393079 | Author: wjh033 | Hits:

[SourceCode] FPGA信号发生多波形程序

Description: FPGA的DDS的HDL程序，还有生成的波形MIF表
Platform: | Size: 14833714 | Author: jxa2010 | Hits:

[Communication] Project1-DDS

Description: 直接频率和成DDS，可以在Altera的FPGA下载实现-directly into DDS frequency and can be downloaded from Altera FPGA Implementation
Platform: | Size: 8192 | Author: lf | Hits:

Description: 本程序功能: DDS文件夹内的程序，完成直接数字频率合成功能,有正弦,三角,方波三种波形,并能扫频. 可通过键盘操作设置频率参数和选择波形种类和控制运行. 由两部分组成,"C"文件夹内,是用于在 51 单片机上运行的 C语言程序, "Verilog"文件夹内,是用Verilog语言编写的 FPGA 程序.-this program functions : DDS folder procedures, complete direct digital frequency synthesis, sine, triangle, Three square waveform, and can sweep. can be set up through the keyboard operation frequency waveform parameters and the types of choice and control operations. composed of two parts, "C" folder, for the 51 microcontroller running C Programming Language, "Verilog" folder, use the Verilog language FPGA procedures.
Platform: | Size: 1027072 | Author: 吴健 | Hits:

[SCM] FPGA--DDS-PhaseMeasure

Description: Verilog实现的DDS正弦信号发生器和测频测相模块，DDS模块可产生两路频率和相位差均可预置调整的值正弦波，频率范围为20Hz-5MHz，相位范围为0°-359°，测量的数据通过引脚传输给单片机，单片机进行计算和显示。-Verilog realize the DDS sine wave signal generator and frequency measurement module test phase, DDS module can generate both frequency and phase difference can be preset to adjust the value of sine wave, frequency range of 20Hz-5MHz, phase range of 0 °-359 ° , measurement data and transmit them to the single-chip pin, single-chip microcomputer to calculate and display.
Platform: | Size: 1371136 | Author: haoren | Hits:

[VHDL-FPGA-Verilog] DDS-2

Description: 用FPGA实现DDS的原理图，结构清晰，采用总线方式与外部单片机通信-FPGA realization of DDS with the schematic diagram, structural clarity, the use of bus-way communication with the outside Singlechip
Platform: | Size: 13312 | Author: 赵培立 | Hits:

[VHDL-FPGA-Verilog] DDS

Description: DDS的频率转换可以以近似认为是即时的，这是因为它的相位序列在时间上是离散的，在频率控制字改变之后，要经过一个时钟周期之后才能按照新的相位增量增加，所以也可以说它的频率转换时间就是频率控制字的传输时间，-DDS frequency conversion can be considered similar to real-time, this is because it is the phase sequence in time is discrete, in the frequency control word change after one clock cycle to go through before a new phase in accordance with the incremental increase, so it can be said of the frequency switching time is the frequency control word transmission time,
Platform: | Size: 2096128 | Author: lqb | Hits:

[VHDL-FPGA-Verilog] dds

Description: 基于VHDL+FPGA的DDS信号发生设计，已经通过调式-Based on VHDL+ FPGA design of the DDS signal has been through mode
Platform: | Size: 560128 | Author: 陈阳 | Hits:

[VHDL-FPGA-Verilog] FPGA

Description: FPGA，vhdl语言的学习资料； FPGA的简单设计 dds的设计-FPGA, vhdl language learning materials FPGA design of a simple design dds
Platform: | Size: 2098176 | Author: wade | Hits:

[SCM] dds

Description: 关于FPGA中DDS核参数设置的资料，英文版的XILINX资料-DDS on the FPGA in the data set of nuclear parameters, the English version of XILINX information
Platform: | Size: 1664000 | Author: 李晶 | Hits:

[Books] dds

Description: FPGA实现DDS，f=90kHZ~5MHZ范围-FPGA realization of DDS, f = 90kHZ ~ 5MHZ the scope of
Platform: | Size: 1442816 | Author: 王勤 | Hits:

[VHDL-FPGA-Verilog] dds

Description: fpga利用dds原理，产生正弦波，简单实用，成本低-fpga using dds principle, have a sine wave
Platform: | Size: 571392 | Author: wangjian | Hits:

[SCM] dds

Description: DDS文件夹内的程序，完成直接数字频率合成功能,有正弦,三角,方波三种波形,并能扫频. 可通过键盘操作设置频率参数和选择波形种类和控制运行. 由两部分组成,"C"文件夹内,是用于在 51 单片机上运行的 C语言程序, "Verilog"文件夹内,是用Verilog语言编写的 FPGA 程序-ewfreytrgrwf reggwrter rgterthhrgdfs rgdgf egrthg rgreaf rtgerf srfefsf frafgsf frghrsrgwgt
Platform: | Size: 28672 | Author: nbonwenli | Hits:

[VHDL-FPGA-Verilog] dds

Description: 基于FPGA的DDS设计，本程序采用verilog HDL语言编写，使用DDS+Pll倍频-The DDS-based FPGA design, the procedures used verilog HDL language, the use of DDS+ Pll frequency
Platform: | Size: 190464 | Author: 赵一 | Hits:

[Program doc] FPGA-DDS-FM

Description: DDS 调频信号发生器框图设计原理，有仿真测试结果-DDS signal generator FM Design Principle diagram
Platform: | Size: 69632 | Author: chenjiwei | Hits:

[VHDL-FPGA-Verilog] DDS

Description: 基于Verilog的dds设计，已经经过调试，可直接使用-Dds of Verilog-based design, has been testing can be used directly
Platform: | Size: 2041856 | Author: 郭帅 | Hits:

[SCM] DDS

Description: 基于FPGA的DDS程序，可产生任意频率任意相位的波形-FPGA-based DDS program, can generate any frequency arbitrary waveform phase
Platform: | Size: 2971648 | Author: juan | Hits:

[SCM] dds

Description: 基于单片机与FPGA的DDS程序代码，产生任意波形-DDS-based MCU with FPGA-code, resulting in arbitrary waveform
Platform: | Size: 345088 | Author: jiangjun | Hits:

[VHDL-FPGA-Verilog] dds-design

Description: fpga实现dds，实现任意波形输出信，设计代码verilog-dds fpga realization
Platform: | Size: 1024 | Author: cc | Hits:

[VHDL-FPGA-Verilog] FPGA-VHDL-DDS

Description: 基于FPGA的DDS波形发生器--程序，如果需要产生输出不同的位数的波形，可以自行修改程序中的rom表中数据位数-FPGA-based waveform generator DDS- procedure, if the number of bits required to generate output of different waveforms in the program can modify data in the table the median rom
Platform: | Size: 1256448 | Author: 许聪 | Hits:

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[VHDL-FPGA-Verilog] 基于FPGA的数字频率计

[SourceCode] FPGA信号发生多波形程序

[Communication] Project1-DDS

[SCM] DDS+51

[SCM] FPGA--DDS-PhaseMeasure

[VHDL-FPGA-Verilog] DDS-2

[VHDL-FPGA-Verilog] DDS

[VHDL-FPGA-Verilog] dds

[VHDL-FPGA-Verilog] FPGA

[SCM] dds

[Books] dds

[VHDL-FPGA-Verilog] dds

[SCM] dds

[VHDL-FPGA-Verilog] dds

[Program doc] FPGA-DDS-FM

[VHDL-FPGA-Verilog] DDS

[SCM] DDS

[SCM] dds

[VHDL-FPGA-Verilog] dds-design

[VHDL-FPGA-Verilog] FPGA-VHDL-DDS

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