Search - FPGA ME

[Other] FPGA-MCU

Description: 介绍如何用单片机配置FPGA，仅供参考，如有疑问请联系我。-how to use microcontroller FPGA configuration, for reference purposes only, if any questions, please contact me.
Platform: | Size: 55437 | Author: 曾仁良 | Hits:

[Other resource] motioncontrol

Description: 这是一个采用FPGA实现PCI接口的运动控制卡，全部实现的论文资料，是我的硕士毕业论文，请指正，-using FPGA PCI Motion Control Card, all of the papers, I have a master's degree thesis, please correct me, thank you
Platform: | Size: 276423 | Author: 秦矜 | Hits:

[Other] motioncontrol

[DSP program] AD9280

Description: 献给有需要的朋友，找资料太耗时间了，希望你们能够尽快找到我这份。-Have the needs of dedicated friends, the amount of time spent looking for information too, and I hope that you will be able to find me this.
Platform: | Size: 339968 | Author: wanwenqing | Hits:

[VHDL-FPGA-Verilog] Des2Sim

Description: 本文介绍了一个使用 VHDL 描述计数器的设计、综合、仿真的全过程，作为我这一段时间自学 FPGA/CPLD 的总结，如果有什么不正确的地方，敬请各位不幸看到这篇文章的大侠们指正，在此表示感谢。当然，这是一个非常简单的时序逻辑电路实例，主要是详细描述了一些软件的使用方法。文章中涉及的软件有Synplicity 公司出品的Synplify Pro 7.7.1； Altera 公司出品的 Quartus II 4.2；Mentor Graphics 公司出品的 ModelSim SE 6.0。 -This article describes a VHDL description of the use of counter design, synthesis, simulation of the entire process, this time as my self-FPGA/CPLD summary, if what has not the right place, please see this article that, unfortunately, the heroes They correct me, wish to express my gratitude. Of course, this is a very simple example of sequential logic circuit is mainly a detailed description of a number of software usage. Article involved in the software company has produced Synplicity
Platform: | Size: 1945600 | Author: 黄鹏曾 | Hits:

[VHDL-FPGA-Verilog] Example-b3-1

Description: ALTER FPGA/GPLD设计（初级篇）的源码，只是其中的一部分供大家参考，如果还有用到其他的，请联系我-ALTER FPGA/GPLD design (primary chapter) of the source, is only one part of it for public consultation, if there are other uses, please contact me
Platform: | Size: 872448 | Author: 宋振丰 | Hits:

[VHDL-FPGA-Verilog] VGA_move

Description: 基于FPGA的控制显示器程序。通过VHDL编程，下载到FPGA实验箱上。-FPGA-based process control monitor. Through the VHDL program, downloaded to test me on the FPGA.
Platform: | Size: 359424 | Author: 王瑀 | Hits:

[VHDL-FPGA-Verilog] cf_fir_latest.tar

Description: It is a fir to implement in a FPGA. It s not desenvolved for me it is a good work of another person
Platform: | Size: 189440 | Author: Tiago | Hits:

[Software Engineering] TheResearchoftherealtimesignalprocessingofSARbased

Description: 3．完成系统的FPGA程序开发与调试，主要包括FFT，IFFT，CMUL和转置存储控制等模块，在此基础上，重点介绍了一种基于DDR SDRAM的行写行读高效转置存储算法，在采用该算法进行转置存储操作时，读写两端的速度相匹配，满足流水线操作要求，提高了整个系统的实时性。最后介绍了采用CORDIC算法实现复图像求模运算的方法，分析了算法的硬件实现结构，并给出了基于FPGA 的实现方法及仿真结果。-he FPGA s development and debugging are implemented,including FFT, IFFT, CMUL and C0ntrol of CTM．Based Oll this，Implementation of a high efficient corner turn memory arithmetic with writing and reading by row based on DDR SDRAM is introduced．When using CTM with this algorithm，me speed of reading and writing maItches and meets the requirement of pipelined operation．Finally a method of model implementation for complex image based on CORDIC algorithm is introduced．The algorithm’s hardware implementation structure is analysed, and implementation methodology and simulation results are given
Platform: | Size: 5155840 | Author: mabeibei | Hits:

[File Format] mux4x1

Description: mux 4x1 designed by me in fpga adv pro
Platform: | Size: 4096 | Author: zacri233 | Hits:

[VHDL-FPGA-Verilog] cordic_new

Description: Cordic with very high resolution. This program is developped by me. the maximal error is 0.04. You can use it for angle calculation.-Cordic with very high resolution. This program is developped by me. the maximal error is 0.04. You can use it for angle calculation. This original program can be seen in the book: digital processing with FPGA (Uwe Baese), the disadvantage is that the logic cells increases with iteration steps. You can also try this program using state machine instead of this pipeline.
Platform: | Size: 1024 | Author: 包一明 | Hits:

[VHDL-FPGA-Verilog] 86verilog

Description: 以FPGA 芯片为平台构建了数字信号滤波实时处理模块, 给出了 50Hz 陷波器的切比雪夫Ê 型 IIR 数字滤波器 4 阶级联的结构, 提出了对滤波器系数量化的逼近方法, 完成了基于 FPGA 的陷波器实现, 并成功地实现了对含有工频 50Hz 噪声干扰的心电信号的滤波处理, 通过与M at lab 计算所得到的滤波处理效果进行比较分析, 结果表明: 基于FPGA 采用切比雪夫Ê 型 4 级级联结构的 IIR 数字滤波器的误差满足设计要求-　W ith the development of the techno logy of VL S I, the techno logy fo r digital signal p rocessing has developed rap idly . In th is paper, the arch itecture of 50Hz four th2 o rder Chebyshev′ s ModelÊ digital f ilter is show n . In the same t i me, themethod fo r f ilter coeff icient quant if icat i on is p resented . How ever, the f ilter based on FPGA is i mp lemented . The f ilter can p rocess digital signal successfully and its perfo rmance sat isf ies w ith design requirement .
Platform: | Size: 15360 | Author: 任伟 | Hits:

[VHDL-FPGA-Verilog] Hua-wei-FPGA

Description: 华为FPGA设计全套，我导师做课题时候给我的。-Huawei complete FPGA design, when I do the subject mentor to me.
Platform: | Size: 9699328 | Author: dashan | Hits:

[VHDL-FPGA-Verilog] clock

Description: 一个简单的FPGA时钟，里面有PDF说明~-A simple clock sample. There exists a PDF statement files in it. If there exists any problem please contact me.
Platform: | Size: 21504 | Author: chobits | Hits:

[VHDL-FPGA-Verilog] MD5Transform

Description: 本人设计的一个基于FPGA平台用verilogHDL设计的MD5加密，供FPGA学习者学习参考-a MD5 encoder designed by me.It s a learning code for FPGA learner
Platform: | Size: 14491648 | Author: Gevy | Hits:

[VHDL-FPGA-Verilog] nios2_flowwater

Description: 经典的nios2小例程，学习nios入门的经典例程。有疑问可登陆http://hongqinfpga.taobao.com/联系我，本人专门研究fpga嵌入式，欢迎朋友们一起加入学习。-Classic the nios2 small routines, learning the nios entry classic routines. Questions can visit http://hongqinfpga.taobao.com/ contact me, I specialize in the fpga Embedded and friends are welcome to join the learning.
Platform: | Size: 7107584 | Author: 权利红 | Hits:

[VHDL-FPGA-Verilog] NAND_flash_verilog_vhdl

Description: 很好的NAND Flash 硬件驱动语言，支持VHDL和verilog 语言方便移植，如果有想用FPGA直接驱动NAND flash而又不知如何下手的朋友肯定喜欢。- NAND Flash Controller Reference Design =============================================================================== File List 1. RD1055/doc/rd1055.pdf --> NAND Flash Controller Reference Design document RD1055/doc/rd1055_readme.txt --> Read me file (this file) 2. RD1055/Project/nand_flash_cntl.lpf --> preference file for the design RD1055/Project/nfcm_tb_vhd.udo_example --> vital glitch removal example 3. /RD1055/simulation/verilog/rtl_verilog.do --> verilog rtl simulation script /RD1055/simulation/verilog/timing_verilog.do --> verilog timing simulation script /RD1055/simulation/vhdl/rtl_verilog.do --> vhdl rtl simulation script /RD1055/simulation/vhdl/timing_verilog.do --> vhdl timing simulation script 4. RD1055/source/verilog/ACounter.v --> sourc
Platform: | Size: 1192960 | Author: cuiwei | Hits:

[Other Games] Ekran

Description: It is an Arkanoid game that is written by me in VHDL language. ı t is possible to play it via an altera FPGA and a monitor.
Platform: | Size: 10182656 | Author: Kaan Mutlu | Hits:

[VHDL-FPGA-Verilog] ram_2

Description: 双端口RAM，可读，可写，用Verilog编写。希望与大神交流，求大神指正。(Dual port RAM, readable and writable, written in Verilog. Hope to communicate with great God, ask God to correct me)
Platform: | Size: 11412480 | Author: 么么哒哈123 | Hits:

[VHDL-FPGA-Verilog] SOLUTION_FOURIRER OPTICS

Description: thi is the last airbender me so alone
Platform: | Size: 560128 | Author: fbyr | Hits:

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