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[VHDL-FPGA-Verilog] plldigitalclock

Description: 此文件是FPGA中数字时钟开发，包括时钟的分拼 ，备品-file is a digital clock FPGA development, including the sub-clock fight, spare
Platform: | Size: 1024 | Author: liu | Hits:

[Communication-Mobile] DDS+PLL

Description: 基于FPGA的新的DDS+PLL时钟发生器-FPGA-based new DDS PLL clock generator
Platform: | Size: 145408 | Author: 李敏 | Hits:

[VHDL-FPGA-Verilog] FIFO_BEFORE

Description: 是基于fpga的FIFO乒乓操作，后面是与SDRAM接口的，这样主要方便sdram的刷新-fpga is based on the FIFO Table Tennis operation, and is behind SDRAM interface, This major update to the convenience sdram
Platform: | Size: 211968 | Author: eva | Hits:

[Software Engineering] xp2syscloclkpll

Description: 这个是讲pll的具体用法的,一般在fpga设计中都会用到 他,这个是lattice的xp2的pll的介绍,不过,fpga 都是相通的其他两家也差不多-Pll say this is the specific usage, the general design in the FPGA will use him, this is the lattice of the pll of xp2 introduction, however, fpga are connected to other two similar
Platform: | Size: 641024 | Author: | Hits:

[VHDL-FPGA-Verilog] pll

Description: fpga中pll时钟实现的源代码，可实现倍频或分频-pll clock in the FPGA to achieve the source code, can be realized or sub-octave frequency
Platform: | Size: 3072 | Author: 张恒 | Hits:

[Embeded-SCM Develop] PLL

Description: 关于在FPGA或CPLD锁相环PLL原理与应用,介绍用FPGA的分频技术.-FPGA or CPLD on the Theory and Application of phase-locked loop PLL, introduce sub-band using FPGA technology.
Platform: | Size: 94208 | Author: yjc | Hits:

[VHDL-FPGA-Verilog] PLL

Description: PLL 时钟模块　　Quartus II平台的简单设计实例　附仿真波形-PLL clock module Quartus II platform attached to a simple design example simulation waveforms
Platform: | Size: 806912 | Author: 许东滨 | Hits:

[Software Engineering] DigitalPLL

Description: 介绍数字锁相环的基本结构,详细分析基于FPGA的数字锁相环的鉴相器、环路滤波器、压控振荡器各部分的实现方法,并给出整个数字锁相环的实现原理图。仿真结果表明,分析合理,设计正确。
Platform: | Size: 432128 | Author: 萝卜 | Hits:

[VHDL-FPGA-Verilog] pll

Description: 用FPGA实现数字锁相环，开发环境为ISE-Using FPGA digital phase-locked loop, development environment for ISE
Platform: | Size: 178176 | Author: 冯勇 | Hits:

[VHDL-FPGA-Verilog] a3951ddd-b7c8-4598-b873-4cefbaf1d211

Description: Altera公司的FPGA器件内带PLL的详细中文使用手册-Altera' s FPGA device PLL with a detailed user manual in Chinese
Platform: | Size: 553984 | Author: chx | Hits:

[Books] PLL

Description: 介绍了一种采用N 先于M 环路滤波器的全数字锁相环的设计实现。这种全数字锁 相环采用了N 先于M 环路滤波器，可以达到滤除噪声干扰的目的。文中讲述了这种全数字锁相环的结构和工作原理，提出了各单元电路的设计和实现方法，并给出了关键部件的VHDI 代码，最后用FPGA 予以实现。-A good reference for The Design and Realization of a Kind of DPLL Using a N before M Loop FiIter
Platform: | Size: 226304 | Author: Reguse | Hits:

[VHDL-FPGA-Verilog] FPGAPLL

Description: FPGA做的PLL 可以使用，比软件自带的省一些资源-PLL can be used FPGA to do more than the software comes with some of the resources of the province,
Platform: | Size: 112640 | Author: 李小虎 | Hits:

[VHDL-FPGA-Verilog] CyclonePLL

Description: Cyclone™ FPGA具有锁相环（PLL）和全局时钟网络，提供完整的时钟管理方案。Cyclone PLL具有时钟倍频和分频、相位偏移、可编程占空比和外部时钟输出，进行系统级的时钟管理和偏移控制。Altera® Quartus® II软件无需任何外部器件，就可以启用Cyclone PLL和相关功能。本文将介绍如何设计和使用Cyclone PLL功能。 PLL常用于同步内部器件时钟和外部时钟，使内部工作的时钟频率比外部时钟更高，时钟延迟和时钟偏移最小，减小或调整时钟到输出（TCO）和建立（TSU）时间。 -Cyclone ™ FPGA with a phase-locked loop (PLL) and the global clock network and provide a complete clock management solution. Cyclone PLL with the clock multiplier and divider, phase offset, programmable duty cycle and the external clock output for system-level clock management and offset control. Altera ® Quartus ® II software does not require any external devices, you can enable the Cyclone PLL and related functions. This article describes how to design and use the Cyclone PLL features. PLL clock devices commonly used in the synchronization of internal and external clock, so that the inner workings of the clock frequency higher than the external clock, clock delay and clock skew minimum, reduce or adjust the clock to the output (TCO) and the establishment of (TSU) time.
Platform: | Size: 553984 | Author: 裴雷 | Hits:

[VHDL-FPGA-Verilog] altpllpll

Description: 用VHDL语言编写的锁相环源代码，可用于配置FPGA，在FPGA中实现ＰＬＬ功能。-VHDL language with PLL source code, can be used to configure the FPGA, PLL function is implemented in the FPGA.
Platform: | Size: 3072 | Author: 王羽翾 | Hits:

[Other] an471

Description: FPGA PLL 分析，包括时序分析-FPGA PLL Analysis
Platform: | Size: 185344 | Author: Chen | Hits:

[VHDL-FPGA-Verilog] PLL

Description: 基于FPGa实现一个数字锁相环，实现时钟恢复，具有较好的通用性。-pll
Platform: | Size: 1024 | Author: 高星 | Hits:

[VHDL-FPGA-Verilog] pll(FPGA)

Description: 利用VHDL语言对FPGA进行锁相环倍频，经调试已经在开发板上实现倍频-The FPGA using VHDL language PLL frequency multiplier, the debug board has been achieved in the development of frequency
Platform: | Size: 361472 | Author: huangshaobo | Hits:

[Embeded-SCM Develop] FPGA-PLL

Description: 基于EP4C6E22C8N芯片的FPGA PLL实验源代码，可以使用-EP4C6E22C8N chip FPGA PLL-based experiment source code, you can use
Platform: | Size: 331776 | Author: 陈都 | Hits:

[VHDL-FPGA-Verilog] pll_self_rst

Description: 用于检测ALTERA FPGA PLL应用中出现的假锁定问题(Used to detect false lock problems in ALTERA FPGA PLL applications)
Platform: | Size: 482304 | Author: njithjw | Hits:

[VHDL-FPGA-Verilog] FPGA分频

Description: xilinx spant6 PLL分频，生成4个不同频率的时钟，实现LED闪烁。(xilinx spant6 PLL frequency division)
Platform: | Size: 1625088 | Author: 早起的虫子 | Hits:
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