CyclonePLL Cyclone ™ FPGA with a phase-locked

Title: CyclonePLL

Category:
VHDL-FPGA-Verilog
Tags:
[WORD]
File Size:
541kb
Update:
2012-11-26
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Uploaded by:
daniel_pei

Description: Cyclone ™ FPGA with a phase-locked loop (PLL) and the global clock network and provide a complete clock management solution. Cyclone PLL with the clock multiplier and divider, phase offset, programmable duty cycle and the external clock output for system-level clock management and offset control. Altera ® Quartus ® II software does not require any external devices, you can enable the Cyclone PLL and related functions. This article describes how to design and use the Cyclone PLL features. PLL clock devices commonly used in the synchronization of internal and external clock, so that the inner workings of the clock frequency higher than the external clock, clock delay and clock skew minimum, reduce or adjust the clock to the output (TCO) and the establishment of (TSU) time.

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