Description: verilog语言编写的FPGA代码。功能为pc机通过epp不断写数到sram中，然后pc发送中断信号打断写过程读取sram中的数据。rar包中包含epp协议，模块文件和测试文件（test）。-Verilog FPGA code languages. Pc machine functions through a number of epp constantly write to the SRAM, and then pc send interrupt signals to interrupt the process of writing to read the data in the SRAM. rar package includes epp agreement, modules and test documents (test). Platform: |
Size: 43008 |
Author:苗苗 |
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Description: sram 控制器的三种实现方案，来自xinlix工程师之手，不可多得-sram controller implementation of the three programs, from the hands of engineers xinlix, rare Platform: |
Size: 6144 |
Author:刘太联 |
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Description: 图像采集、存储控制verilog源代码，fpga控制SAA1117,采集数据存储到sram，仿真编译测试都能通过-Image acquisition, storage, control verilog source code, fpga control SAA1117, collecting data to sram, simulation tests can be compiled by Platform: |
Size: 25600 |
Author:蹇清平 |
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Description: verilog code that can implemented on ACEX1k
FPGA for a SRAM-verilog code that can implemented on ACEX1k
FPGA for a SRAM Platform: |
Size: 221184 |
Author:z |
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Description: verilog编写的读写SRAM的源码，包括sram的读写控制-SRAM read and write verilog source code written in, including the sram to read and write control Platform: |
Size: 1024 |
Author:haha |
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Description: 备注：使用的是VeriLog HDL语言
软件环境xilinx ISE 10.1，硬件：高教仪EXCD-1FPGA电路板。FPGA信号：spartan-3e .
功能编写硬件描述性语言实现FPGA对板上外设SRAM IS61WV51216BLL的读写，通过串口发送到上位机上，使用串口助手显示读取的数据。-Note: Use the VeriLog HDL language software environment xilinx ISE 10.1, hardware: Higher Miriam EXCD-1FPGA circuit boards. FPGA Signal: spartan-3e. Write functional hardware description language implementation of on-board peripherals SRAM IS61WV51216BLL FPGA to read and write, sent to the host computer through the serial port, use the serial Assistant displays the data read. Platform: |
Size: 5120 |
Author:李钿 |
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Description: 语言：VHDL
功能：利用VHDL编程，实现FPGA对SRAMIS61LV24516的读写操作。由于是针对IS61LV24516型号进行读写的，如果不是此型号的SRAM需要对程序进行时序修改。
仿真工具：modelsim
综合工具：quartus -Language: VHDL
function: the use of VHDL programming, FPGA on SRAMIS61LV24516 read and write operations. Because it is read and write for IS61LV24516 model, if not required for this type of SRAM timing of the program changes.
Simulation tools: modelsim
synthesis tool: quartus II Platform: |
Size: 1024 |
Author:huangjiaju |
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Description: 用FPGA实现SRAM读写控制的Verilog代码-SRAM FPGA implementation using Verilog code to read and write control Platform: |
Size: 13312 |
Author:austin |
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Description: 用verilog hdl语言编写的fpga与片外sram 的读写控制-With the verilog hdl language fpga sram chip with read and write control Platform: |
Size: 57344 |
Author:yishuihan |
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Description: Verilog编写FPGA与片外SRAM通信模块，内含源代码，希望对大家有所帮助。-FPGA in Verilog-chip SRAM with communication modules, including source code, we want to help. Platform: |
Size: 428032 |
Author:haby |
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