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[Communication-Mobile] DDS+PLL

Description: 基于FPGA的新的DDS+PLL时钟发生器-FPGA-based new DDS PLL clock generator
Platform: | Size: 145408 | Author: 李敏 | Hits:

[VHDL-FPGA-Verilog] DDS

Description: 基于ＦＰＧＡ平台，实现了直接数字频率合成。-FPGA-based platform, to achieve a direct digital frequency synthesis.
Platform: | Size: 827392 | Author: liqijun | Hits:

[Program doc] DDS

Description: FPGA中实现基于查找表方式（LUT）的DDS实现，可用在数字下变频和COSTAS锁相环中，Verilog编写，本人已经调通-In FPGA-based lookup table approach (LUT) to achieve the DDS can be used in the digital down-conversion and COSTAS PLL, Verilog prepared, I have transferred Qualcomm
Platform: | Size: 148480 | Author: | Hits:

[VHDL-FPGA-Verilog] Wave_ROM

Description: 基于RAm的FPGA实现DDS,有测试文件-Ram realize the FPGA-based DDS, have the test paper
Platform: | Size: 5120 | Author: xsj | Hits:

[VHDL-FPGA-Verilog] dds

Description: 基于飓风1 fpga 和stc单片机的dds信号源 程序是自己些的 能用 最大频率是2M-1 fpga based on the hurricane and STC dds SCM signal source more of their own can use the maximum frequency is 2M
Platform: | Size: 362496 | Author: 阿斯顿 | Hits:

[VHDL-FPGA-Verilog] dds

Description: 基于VHDL+FPGA的DDS信号发生设计，已经通过调式-Based on VHDL+ FPGA design of the DDS signal has been through mode
Platform: | Size: 560128 | Author: 陈阳 | Hits:

[Software Engineering] dds

Description: 基于FPGA的双路可移相任意波形发生器 Altera中国大学生电子设计文章竞赛获奖作品刊登-FPGA-based dual phase shifter can be arbitrary waveform generator Altera China Undergraduate Electronic Design Contest winning entries published articles
Platform: | Size: 1695744 | Author: 姜兆刚 | Hits:

[VHDL-FPGA-Verilog] FPGA-basedhigh-performance32-bitfloating-pointnucl

Description: 基于FPGA的高性能32位浮点FFTIP核的开发，适合fpga工程技术人员参考-FPGA-based high-performance 32-bit floating-point nuclear FFTIP development, engineering and technical personnel for reference fpga
Platform: | Size: 7507968 | Author: bonjour | Hits:

[VHDL-FPGA-Verilog] dds

Description: 基于FPGA的DDS设计，本程序采用verilog HDL语言编写，使用DDS+Pll倍频-The DDS-based FPGA design, the procedures used verilog HDL language, the use of DDS+ Pll frequency
Platform: | Size: 190464 | Author: 赵一 | Hits:

[VHDL-FPGA-Verilog] DDS

Description: 基于Verilog的dds设计，已经经过调试，可直接使用-Dds of Verilog-based design, has been testing can be used directly
Platform: | Size: 2041856 | Author: 郭帅 | Hits:

[SCM] DDS

Description: 基于FPGA的DDS程序，可产生任意频率任意相位的波形-FPGA-based DDS program, can generate any frequency arbitrary waveform phase
Platform: | Size: 2971648 | Author: juan | Hits:

[SCM] dds

Description: 基于单片机与FPGA的DDS程序代码，产生任意波形-DDS-based MCU with FPGA-code, resulting in arbitrary waveform
Platform: | Size: 345088 | Author: jiangjun | Hits:

[VHDL-FPGA-Verilog] dds

Description: 基于FPGA的直接数字频率合成器（DDS）的设计-FPGA-based direct digital frequency synthesizer (DDS) design of
Platform: | Size: 1024 | Author: sunshine | Hits:

[VHDL-FPGA-Verilog] DDS-FPGA

Description: 基于FPGA的DDS资料！个人搜集的 可直接编译-FPGA-based DDS information!
Platform: | Size: 6350848 | Author: eva | Hits:

[Software Engineering] DDS-FM-FPGA

Description: DDS介绍,FM信号发生器的设计!基于DDS技术的FM信号发生器的设计及其FPGA实现-DDS introduced, FM Signal Generator! FM signal based on DDS technology and FPGA Implementation Generator
Platform: | Size: 356352 | Author: 雨夜里 | Hits:

[VHDL-FPGA-Verilog] dds

Description: 基于FPGA的DDS波形信号发生器，功能强大，代码规范，值得学习-FPGA-based DDS waveform signal generator, powerful, code specifications, it is worth learning
Platform: | Size: 2561024 | Author: Andy Lao | Hits:

[VHDL-FPGA-Verilog] DDS-STC89C52-DAC0800-FPGA.doc

Description: 电子设计大赛，波形发生器，基于单片机和FPGA的DDS信号源。-Electronic Design Contest, waveform generator, microcontroller and FPGA-based DDS signal source.
Platform: | Size: 1718272 | Author: 刘尚霖 | Hits:

[VHDL-FPGA-Verilog] FPGA-VHDL-DDS

Description: 基于FPGA的DDS波形发生器--程序，如果需要产生输出不同的位数的波形，可以自行修改程序中的rom表中数据位数-FPGA-based waveform generator DDS- procedure, if the number of bits required to generate output of different waveforms in the program can modify data in the table the median rom
Platform: | Size: 1256448 | Author: 许聪 | Hits:

[VHDL-FPGA-Verilog] FPGA-VHDL-DDS

Description: 这是基于FPGA的直接数字频率合成器的程序，是VHDL语言-This is based on FPGA for direct digital frequency synthesizer program that is VHDL language
Platform: | Size: 1253376 | Author: 笙箫 | Hits:

[VHDL-FPGA-Verilog] DDS

Description: 基于FPGA的DDS直接信号合成器，基于Altera CYcloneII系列-DDS direct FPGA-based signal synthesis, based on Altera CYcloneII Series
Platform: | Size: 949248 | Author: 郭强 | Hits:
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