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[VHDL-FPGA-Verilog] counter

Description: 计数器的VHDL设计，已经在FPGA上验证-VHDL counter design, has been tested in the FPGA
Platform: | Size: 1024 | Author: chen | Hits:

[VHDL-FPGA-Verilog] COUNTER

Description: 对外部输入的高频脉冲信号进行分频，应用于FPGA/CPLD .-External input of high-frequency pulse signal frequency, applies to FPGA/CPLD.
Platform: | Size: 1024 | Author: fsdfe | Hits:

[VHDL-FPGA-Verilog] Ripple_Carry_counter

Description: Ripple Carry Counter. the synchronous version of Ripple Counter. a bit less fasr version the ripple counter but a synchronmous one that will work well on FPGA. wrriten in behavioral VHDL.
Platform: | Size: 20480 | Author: avi | Hits:

[VHDL-FPGA-Verilog] counter

Description: 用Verilog HDL语言实现FPGA的频率等精度测量。（已经过验证）-Using Verilog HDL language, such as FPGA frequency measurement accuracy. (Has already been verified)
Platform: | Size: 2582528 | Author: double | Hits:

[VHDL-FPGA-Verilog] db0358fc-1f16-4f07-9f0f-defb77998bb1

Description: fpga实现简单的计数器功能，用vhdl写的，有一个LED-fpga simple counter function
Platform: | Size: 580608 | Author: zx | Hits:

[VHDL-FPGA-Verilog] counter

Description: 适用于FPGA Xilinx开发板的Counter程序，计数从0到9999，在板上用4位7段数码管显示，可实现双向计数。-Applicable to FPGA Xilinx development board of the Counter procedures, counting from 0 to 9999, in the board with four 7 digital display, enabling two-way counts.
Platform: | Size: 131072 | Author: flyingwings | Hits:

[Software Engineering] counter48

Description: 48 bitt counter for fpga
Platform: | Size: 2048 | Author: rrnair | Hits:

[VHDL-FPGA-Verilog] digitalwatch

Description: Describe: This VHDL digital clock, the use of digital control and FPGA design to achieve a number of counter clock, show hours, minutes ,seconds and alarm. The procedure depends on the metric system and consider six decimal counter preparation. The experimental procedure in the source code for a detailed Notes-Describe: This is VHDL digital clock, the use of digital control and FPGA design to achieve a number of counter clock, show hours, minutes ,seconds and alarm. The procedure depends on the metric system and consider six decimal counter preparation. The experimental procedure in the source code for a detailed Notes
Platform: | Size: 92160 | Author: eric carmen | Hits:

[VHDL-FPGA-Verilog] tutorial

Description: 计数器 平台：Xilinx ise 10.1 说明：和ise10.1快速帮助手册配套的源码，适用于初学者。-counter platform: Xilinx ise 10.1 comment: supplement to ise quick start tutorial 10.1, suitable for freshman to fpga and ise software.
Platform: | Size: 310272 | Author: kn | Hits:

[Other] fpganaoz

Description: 基于FPGA闹钟系统的设计。 1.秒模块实际上是一个计数器，一秒记录一次并输出。 2.分，时模块在一个脉冲上升沿计数一次的基础上，加入了时间调整控制。 3.调整时间的控制模块，在使能信号有效时，才可实现时分的调整。 4.闹钟调整及控制模块，可实现闹钟设时的调节功能。 5.显示模块，实现时间与闹钟显示的切换。 6.闹铃模块，实现闹铃的发声装置。 7.总逻辑模块，实现电子闹钟相应功能的总系统。 -FPGA-based alarm system design. 1. Second module is actually a counter, a second recording and output. 2. Am, when the module is a pulse based on the rising edge of a count by adding the time to adjust control. 3. Adjust the time of the control module, the enable signal is active in order to achieve the hours of adjustments. 4. Alarm clock adjustment and control modules can be realized when the alarm clock set up regulatory function. 5. Display module to realize the time and alarm clock display switch. 6. Alarm module to achieve the alarm audible signal devices. 7. The total logic block to realize the corresponding function of the total electronic alarm system.
Platform: | Size: 197632 | Author: maominchao | Hits:

[VHDL-FPGA-Verilog] counter

Description: 基于VHDL的计数代码，可用于FPGA芯片对步进电机的控制-Count based on VHDL code for FPGA chips can be used to control stepper motor
Platform: | Size: 1024 | Author: sun | Hits:

[VHDL-FPGA-Verilog] AVR-FPGA

Description: 电子计数式简易多功能计数器的原理、设计、应用及误差特性。本计数器以ATmega128单片机为控制核心，由FPGA模块、键盘输入模块、液晶显示模块、温度测量模块等功能模块组成，实现了周期、频率、时间间隔的测量等功能。-Achieve multi-counter, you would like to have more detailed
Platform: | Size: 5120 | Author: 乐毅学 | Hits:

[VHDL-FPGA-Verilog] counter

Description: 关于FPGA实现的几种计数器的verilog源程序-FPGA implementation of several counter verilog source code
Platform: | Size: 2048 | Author: 王腾 | Hits:

[VHDL-FPGA-Verilog] count

Description: 一种计数器的FPGA的verilog源程序和仿真图谱-A kind of counter verilog source code and simulation of FPGA-map
Platform: | Size: 100352 | Author: 王腾 | Hits:

[VHDL-FPGA-Verilog] max

Description: 这是一个在MAX+plus上面的计数器仿真图，基于FPGA的仿真。-This is a counter above the MAX+ plus simulation map, FPGA-based simulation.
Platform: | Size: 18432 | Author: 王天刚 | Hits:

[VHDL-FPGA-Verilog] 15th_counter

Description: 用VHDL实现15位计数器,可应用于FPGA,ASIC的开发和应用-VHDL implementation with 15-bit counter can be used for FPGA, ASIC development and application of
Platform: | Size: 1024 | Author: qianli | Hits:

[VHDL-FPGA-Verilog] counter

Description: 用VHDL语言编写COUNTER-FPGA VHDL COUNTER
Platform: | Size: 113664 | Author: CG | Hits:

[VHDL-FPGA-Verilog] counter

Description: 应用FPGA中VHDL语言编写计数器程序-Application of VHDL language preparation FPGA counter program
Platform: | Size: 3072 | Author: xiaoyu | Hits:

[VHDL-FPGA-Verilog] counter

Description: Counter example for FPGA with VHDL
Platform: | Size: 10240 | Author: arza | Hits:

[VHDL-FPGA-Verilog] counter

Description: 基于fpga的倒计时器。 可实现6位数的倒计时，通过按键设置初始值，倒计时结束提醒等功能(An inverted timer based on FPGA)
Platform: | Size: 3165184 | Author: 奈歌 | Hits:
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