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[VHDL-FPGA-Verilog] add_full_n

Description: 该程序实现的是n位全加器，首先用与非门实现一位全家器，最后实现n位的全加器。-the program is to achieve the n-bit full adder, first using the door with non-realization of a family- and finally realize the full n-bit adder.
Platform: | Size: 21504 | Author: 许嘉璐 | Hits:

[Documents] ripple-lookahead-carryselect-adder

Description: Ripple Adder: 16-bit 全加,半加及ripple adder的设计及VHDL程序 Carry Look ahead Adder:4, 16, 32 bits 前置进位加法器的设计方案及VHDL程序 Carry Select Adder:16 Bits 进位选择加法器的设计方案及VHDL程序-Ripple Adder : 16-bit full adder, semi-Canada and the ripple adder design and VHDL procedures Carry Look ahead Adder : 4, 16, 32 bits front rounding Adder and the VHDL design procedures Carry Select Adder : 16 Bits Progressive Choice Adder design and VHDL- sequence
Platform: | Size: 15360 | Author: 李成 | Hits:

[VHDL-FPGA-Verilog] fulleradder

Description: 本程序以Modelsim为开发平台，采用VHDL为开发语言，实现了简单的全加器．适合初学Modelsim的同行-Modelsim the procedures for the development of a platform for the development of VHDL language, achieving a simple full adder. Suitable for a novice counterparts Modelsim
Platform: | Size: 30720 | Author: 刘小军 | Hits:

[Software Engineering] 10vhdlexamples

Description: 10个VHDL程序实例，包括加法器，全加器、函数发生器，选择器等。-10 examples of VHDL procedures, including the adder, full adder, function generator, selector and so on.
Platform: | Size: 41984 | Author: petri | Hits:

[VHDL-FPGA-Verilog] add_1p

Description: 2级流水线实现的8位全加器的VHDL代码，适用于altera系列的FPGA/CPLD-Realize two lines of eight full adder of the VHDL code, applicable to altera series of FPGA/CPLD
Platform: | Size: 1024 | Author: wgx | Hits:

[VHDL-FPGA-Verilog] fadder4

Description: VHDL实现四位全加器，适合初学者，源程序下载-VHDL realization of four full adder, suitable for beginners, the source code download
Platform: | Size: 112640 | Author: 黄利 | Hits:

[Other] FULLADD

Description: Full adder using Verilog
Platform: | Size: 11264 | Author: ying chen | Hits:

[VHDL-FPGA-Verilog] VHDL

Description: 数字系统设计中的全加器、10进制计数器、2-4译码器、摩尔状态机、2-1路选择器的源代码-Digital System Design full adder, 10 hexadecimal counter ,2-4 decoder, Moore state machine ,2-1 MUX source code
Platform: | Size: 901120 | Author: 李帆 | Hits:

[VHDL-FPGA-Verilog] voterandcounter

Description: 用VHDL写的源代码程序，包涵三人表决器，七人表决器，全加器以及模24，模60的计数器，都是单文件的，由于程序小又多，所以集中在一起，供新学习VHDL语言的朋友们参考。-With VHDL source code written procedures, includes three of the voting machine, vote on seven people, and full adder, as well as modulus 24, modulus 60 counters, are single-file, as many small procedures, so together for the new Learning VHDL Language Reference friends.
Platform: | Size: 2048 | Author: 韩笑 | Hits:

[source in ebook] f_adder

Description: 全加器， 全加器-Full-adder, full adder, full adder
Platform: | Size: 102400 | Author: Betty | Hits:

[VHDL-FPGA-Verilog] seven

Description: 这是我在ISP编程实验中独立编写的采用结构化描述的一个七人表决器，通过独特的3次映射一位全加器的方法从而实现七人表决器的功能，与网络上任何其他的七人表决器源码决无雷同。-This is my ISP programming in an independent experiment using a structured, prepared as described in a seven-member voting machine, through a unique 3 times a full adder mapping method in order to achieve a vote of seven functions, with the network on any other A seven-member voting machine source code must not identical.
Platform: | Size: 84992 | Author: daisichong | Hits:

[Windows Develop] fulladder

Description: full adder. dai jinwei de liangwei quan jiaqi-fulladder
Platform: | Size: 1024 | Author: aaaaaaa7 | Hits:

[VHDL-FPGA-Verilog] add

Description: 一位全加器源码实现了MAX及其一系列器件实现全加的功能-A full adder and its source code to achieve the MAX series of devices to achieve the functions of the All-Canadian
Platform: | Size: 13312 | Author: yigezi | Hits:

[Other] adder17

Description: 实现17位加法，利用一个16位超前进位加法器和一个一位全加器构成的一个有进位输入和进位输出的17加法器，并且16位加法器利用的使四位超前进位加法器构成。它在booth乘法器设计中经常用到。可以使初学者对模块的调用了解更加透彻。-Adder 17 to achieve the use of a 16-bit CLA, and a one-bit full adder composed of a binary input and binary output of the adder 17, and 16-bit adder to make use of four CLA pose. Multiplier in the booth design frequently used. Modules will enable beginners to a more thorough understanding of the call.
Platform: | Size: 2048 | Author: htpq | Hits:

[MiddleWare] ADDER

Description: 本设计是用32位的并行全加器的,可以实现浮点运算!-The design is a parallel 32-bit full adder, and floating-point operations can be achieved!
Platform: | Size: 278528 | Author: 王强 | Hits:

[Other] add4bit

Description: 一位全加器的VHDL源码与TEST BENCH.XILINX下通过-A full adder and the VHDL source code through TEST BENCH.XILINX
Platform: | Size: 813056 | Author: 祁才君 | Hits:

[VHDL-FPGA-Verilog] adder

Description: 一位全加器可由两个一位半加器与一个或门构成，该设计利用层次结构描述法，首先设计半加器电路，将其打包为半加器模块；然后在顶层调用半加器模块组成全加器电路-A full adder can be two a half-adder and an OR gate structure, the design is the use of hierarchical description method, first of all the design half-adder circuit, be packaged as a half-adder module and then call at the top half-adder composed of full-adder circuit modules
Platform: | Size: 157696 | Author: 哈哈 | Hits:

[VHDL-FPGA-Verilog] four_adder

Description: 应用一位全加器的VHDL语言，创建一位全加器符号，用原理图完成四位全加器-Application of a full adder VHDL language, to create a full-adder symbol, with the principle of the completion of four full adder diagram
Platform: | Size: 149504 | Author: 安博 | Hits:

[VHDL-FPGA-Verilog] addersandsubtractors

Description: this project is based on half adder ,full adder,half subtractor and full subtractor using vhdl.this is the 100 correct code,reference is taken from book digital electrionics written by anand kumar.please use quatrus to access this code.this code can be used for the final year project for engineering. Here dataflow techniques and behavioural techniques are used. - this project is based on half adder ,full adder,half subtractor and full subtractor using vhdl.this is the 100 correct code,reference is taken from book digital electrionics written by anand kumar.please use quatrus to access this code.this code can be used for the final year project for engineering. Here dataflow techniques and behavioural techniques are used.
Platform: | Size: 65536 | Author: jatab | Hits:

[VHDL-FPGA-Verilog] 2-bit-full-adder-master

Description: full adder 4 bit one you
Platform: | Size: 2048 | Author: Danh | Hits:
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