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[GUI Develop] gate

Description: 一个简单的c++桌面模型，gate模型的简单构造，仅供参考
Platform: | Size: 586315 | Author: wendell | Hits:

[Embeded-SCM Develop] GATE

Description: 楼宇可视对讲门口机C语言源程序，以及AT89X系列芯片的祥细资料。-source code of interphone/door entry system and document of AT89X
Platform: | Size: 2325504 | Author: 汪锋 | Hits:

[Other] transistor10

Description: 闸流管和双向可控硅应用的十条黄金原则---硬件电路设计经典。-gate and the two-way flow of the application of SCR 10 gold principle--- hardware circuit design classic.
Platform: | Size: 574464 | Author: lsj | Hits:

[Other] execRing0CodebyAnyUserMode

Description: 众所周知在非 Admin 用户模式下，是不允许加载驱动执行 RING 0 代码的。本文提供了一种方法，通过修改系统 GDT，IDT 来添加自己的 CALLGATE 和 INTGATE 这样便在系统中设置了一个后门。我们就可以利用这个后门在任意用户模式下执行 ring 0 代码了。为了保证我们添加的 CALLGATE 和 INT GATE 永久性。可以在第一次安装时利用 SERVICE API 或 INF 文件设置成随系统启动。不过此方法也有个缺陷，就是在第一次安装 CALLGATE 或 INTGATE 时仍然需要 ADMIN 权限。下面分别给出了添加 CALLGATE 与 INTGATE 的具体代码。 -As is well known in the non-Admin user mode, is not allowed to drive the implementation of load code RING 0. This article provides a method by modifying the system, GDT, IDT to add your own CALLGATE and INTGATE this way in the system set up a backdoor. We can use this backdoor in any user mode implementation of ring 0 code. In order to ensure we add CALLGATE and INTGATE permanent. Can be installed in the first use of SERVICE API or INF file with the system set to start. But this method also has a defect is first installed CALLGATE or INTGATE still need ADMIN privileges. , Respectively, are given below to add CALLGATE with INTGATE specific code.
Platform: | Size: 4096 | Author: Michael | Hits:

[GUI Develop] gate

Description: 一个简单的c++桌面模型，gate模型的简单构造，仅供参考-A simple c++ Desktop model, gate model of simple construction, is for reference only
Platform: | Size: 585728 | Author: wendell | Hits:

[VHDL-FPGA-Verilog] gate

Description: verilog中调用门级电路的实验程序，实现了门级舰模-call Verilog gate-level circuit of the experimental procedures, to achieve a gate-level ship-mode
Platform: | Size: 169984 | Author: 洪磊 | Hits:

[Other] Log_Shifter_Gate_Level_Design

Description: Log Shifter Gate Level Design using Verilog(IC design Lab) and Lab Note
Platform: | Size: 2929664 | Author: eknngx | Hits:

[Other] Clock_Gating

Description: 本文重点详细讲述了gate clock的用法和设计-In this paper, the focus of a detailed account of the gate clock usage and design
Platform: | Size: 30720 | Author: 子墨 | Hits:

[VHDL-FPGA-Verilog] VHDLcode_gate

Description: different gate implementations
Platform: | Size: 2048 | Author: judy | Hits:

[VHDL-FPGA-Verilog] and_gate

Description: And gate testbench, testbench to simulate and run in modelsim
Platform: | Size: 5120 | Author: Leo | Hits:

[VHDL-FPGA-Verilog] FPGA_design_part1

Description: FPGA是英文Field Programmable Gate Array的缩写，即现场可编程门阵列，它是在PAL、GAL、EPLD等可编程器件的基础上进一步发展的产物。-FPGA is the English acronym for Field Programmable Gate Array, or field programmable gate arrays, it is in PAL, GAL, EPLD and other programmable devices based on the further development of the product.
Platform: | Size: 4754432 | Author: 刘超 | Hits:

[OS program] key

Description: 调用门键盘记录程序编写 :)enjoy it-Call gate keyloggers write:) enjoy it
Platform: | Size: 82944 | Author: 刘阳 | Hits:

[SCM] pacb_speed

Description: 使用PACB方式测试脉冲的程序，主要和光电门一起使用，用于测速-PACB at testing the use of pulse procedure, used in conjunction with the principal and optical gate for speed
Platform: | Size: 515072 | Author: Arthur | Hits:

[Other] high_speed

Description: 高速数字电路设计教材，包括：基本原理；逻辑门的高速特性；测量方法；传输线；地平面和层堆积等-High-speed digital circuit design materials, including: basic principles logic gate, high-speed characteristics measurement methods transmission line ground plane and layer stacking, etc.
Platform: | Size: 4646912 | Author: 姚龙海 | Hits:

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[GUI Develop] gate

[Embeded-SCM Develop] GATE

[Other] transistor10

[Other] execRing0CodebyAnyUserMode

[GUI Develop] gate

[VHDL-FPGA-Verilog] gate

[Other] Log_Shifter_Gate_Level_Design

[Other] Clock_Gating

[VHDL-FPGA-Verilog] VHDLcode_gate

[VHDL-FPGA-Verilog] and_gate

[VHDL-FPGA-Verilog] FPGA_design_part1

[OS program] key

[SCM] pacb_speed

[Other] high_speed

[Education soft system] Backpropagation

[VHDL-FPGA-Verilog] gate

[Embeded Linux] gate

[Communication-Mobile] DSSS_enhanced_with_a_coarse_time_synchronization_l

[Other] GATE-2017-QuestionsEE-Session1-Engg-Academy

[Other] gate driver circuits from fuji

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