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[VHDL-FPGA-Verilog] 数字系统设计相关

Description: 这是有关VHDL的相关源代码，有简易CPU、加法器、除法器、计数器等-This is the relevance of the VHDL source code, a simple CPU, Adder, Divider, counters, etc.
Platform: | Size: 45056 | Author: 刘建 | Hits:

[VHDL-FPGA-Verilog] Verilog_FPGA_fp

Description: 用Verilog实现基于FPGA的通用分频器-using Verilog FPGA-based Universal Frequency Divider
Platform: | Size: 124928 | Author: xiong | Hits:

[MPI] sdgshjd

Description: 数字系统设计这是有关的相关源代码，有简易CPU 除法器、计数器等 ...[fpdiv_vhdl.rar] - 四位除法器的vhdl源程序 [vhdl范例.rar] - 最高优先级编码器8位相等比较器 三人表决器（三种不同的描述方式） 加法器描述 8位总线收发器：74245 （注2） 地址译码（for m68008） 多路选择器（使 BR> ... -Digital System Design This is the underlying source code, a simple CPU divider. Counter etc. ... [fpdiv_vhdl.rar]- 4 division of vhdl source [vh dl example. rar]- highest priority encoder compared to eight for phase three of the vote (the three different description ) Adder Description eight bus transceiver : 74245 (Note 2) address decoder (for m68008) Multiple choice (so that BR
Platform: | Size: 1024 | Author: 张瑞 | Hits:

[VHDL-FPGA-Verilog] divider

Description: 介绍了除法器的设计，采用verilogHDL语言，利用modelsim仿真验证，压缩包中包含了流程图-Introduced the divider design, using verilogHDL language, the use of ModelSim simulation, compressed package that contains a flow chart
Platform: | Size: 83968 | Author: yaoyongshi | Hits:

[VHDL-FPGA-Verilog] div2

Description: 32位除法器 被除数和除数均为16位整数，16位小数 商为32位整数，16位小数 余数为16位整数，16位小数 Verilog HDL 代码-32 divider dividend and divisor are 16-bit integer, decimal 16 for the 32-bit integer, 16-bit decimal number more than 16 integer, 16-bit decimal Verilog HDL code
Platform: | Size: 1024 | Author: 李春阳 | Hits:

[VHDL-FPGA-Verilog] Frequency_divider

Description: 用VERILOG HDL实现的任意 频率分频器源代码，是一个通用的程序-With VERILOG HDL realize arbitrary frequency divider source code, is a generic procedure
Platform: | Size: 134144 | Author: 洪磊 | Hits:

[VHDL-FPGA-Verilog] c18_divider

Description: 精通verilog HDL语言编程源码之4--常用除法器设计-Proficient in language programming verilog HDL source of 4- Common divider design
Platform: | Size: 1024 | Author: 李平 | Hits:

[VHDL-FPGA-Verilog] div16

Description: 十六位的除法器，采用verilog hdl-16 of the divider using verilog hdl
Platform: | Size: 3072 | Author: 江浩 | Hits:

[VHDL-FPGA-Verilog] divide

Description: Verilog hdl语言的常用除法器设计，可使用modelsim进行仿真-Commonly used languages Verilog hdl divider design, can use the ModelSim simulation
Platform: | Size: 2048 | Author: 许立宾 | Hits:

[VHDL-FPGA-Verilog] clock

Description: verilog HDL 编写的时钟分频器-prepared by the clock divider verilog HDL
Platform: | Size: 672768 | Author: luoxs | Hits:

[VHDL-FPGA-Verilog] Chapter6-9

Description: 第六章到第九章的代码 本书通过100多个模块实例，详细地讲解了Verilog HDL程序设计语言，全书共分13章，内容涉及VerilogHDL语言基本概念、建模、同步设计、异步设计、功能验证等，实例包括各种加法器/计数器、乘法器/除法器、编码器/译码器、状态机、SPIMaster Controller、I2C Master controller、CAN ProtocolController、Memory模块、JPEG图像压缩模块、加密模块、ATA控制器、8位RISC-CPU等及各个实例模块相应的Testbench，所举实例具有很强的实用性和代表性，每个实例均给出了介绍、功能分析、程序代码和结果演示。-Chapter VI to Chapter IX of the code in this book through more than 100 module instance, explain in detail the Verilog HDL programming language, the book is divided into 13 chapters, covering basic concepts VerilogHDL languages, modeling, synchronous design, asynchronous design, functional verification, etc. Examples include a variety of adder/counter, multiplier/divider, encoders/decoders, state machines, SPIMaster Controller, I2C Master controller, CAN ProtocolController, Memory modules, JPEG image compression module, encryption module, ATA controller, 8-bit RISC-CPU, etc. and the various instances of the corresponding module Testbench, The examples are highly practical and representation, each instance of it all gives the introduction, functional analysis, program code and results presentation.
Platform: | Size: 6281216 | Author: xiao | Hits:

[VHDL-FPGA-Verilog] Chapter11-13

Description: 第十一章到第十三章的代码 本书通过100多个模块实例，详细地讲解了Verilog HDL程序设计语言，全书共分13章，内容涉及VerilogHDL语言基本概念、建模、同步设计、异步设计、功能验证等，实例包括各种加法器/计数器、乘法器/除法器、编码器/译码器、状态机、SPIMaster Controller、I2C Master controller、CAN ProtocolController、Memory模块、JPEG图像压缩模块、加密模块、ATA控制器、8位RISC-CPU等及各个实例模块相应的Testbench，所举实例具有很强的实用性和代表性，每个实例均给出了介绍、功能分析、程序代码和结果演示。-Chapter XI to the 13th chapter of the code in this book through more than 100 module instance, explain in detail the Verilog HDL programming language, the book is divided into 13 chapters, covering basic concepts VerilogHDL languages, modeling, synchronous design, asynchronous design, functional verification, etc. Examples include a variety of adder/counter, multiplier/divider, encoders/decoders, state machines, SPIMaster Controller, I2C Master controller, CAN ProtocolController, Memory modules, JPEG image compression module, encryption module, ATA controller, 8-bit RISC-CPU, etc. and the various instances of the corresponding module Testbench, The examples are highly practical and representation, each instance of it all gives the introduction, functional analysis, program code and results presentation.
Platform: | Size: 5088256 | Author: xiao | Hits:

[VHDL-FPGA-Verilog] clk_div

Description: ＦＰＧＡ　Ｖｒｉｌｏｇ　ＨＤＬ　分频器　输入３３ＭＨＺ　，输出１ＫＨＺ－５０ＨＺ-FPGA Vrilog HDL divider input 33MHZ, output 1KHZ-50HZ
Platform: | Size: 5099520 | Author: 魏杰 | Hits:

[VHDL-FPGA-Verilog] divider

Description: verilog HDL编写的浮点除法器，编译通过，可综合。压缩包包含三个文件。-verilog HDL write floating-point divider, compile, can be integrated. Archive contains three files.
Platform: | Size: 2048 | Author: 韩冰 | Hits:

[VHDL-FPGA-Verilog] verilog-HDL-Divider

Description: 两个3位二进制数的除法，结果（整数商）输出到数码管显示-Division, the result (integer quotient of two 3-bit binary number) output to the digital display
Platform: | Size: 1024 | Author: moxiaolin | Hits:

[VHDL-FPGA-Verilog] divider

Description: 位数可以任意修改的除法器，本人亲自测试，可以使用，效率和使用资源都是很少的-its a very good divider based on Verilog HDL
Platform: | Size: 1024 | Author: 陈成 | Hits:

[VHDL-FPGA-Verilog] frequency-divider

Description: 用VERILOG 语言写的数控分频器，可能输入时钟信号实现任意整数倍的分频，-NC divider, with the words written in VERILOG HDL, can achieve any integer multiple of the input clock frequency, contains the entire project file.
Platform: | Size: 491520 | Author: zyb | Hits:

[e-language] Verilog-HDL

Description: 本课程设计在EDA开发平台上利用Verilog HDL语言设计数控分频器电路，利用数控分频的原理设计乐曲硬件演奏电路，并定制LPM-ROM存储音乐数据，-This course is designed to take advantage of the EDA Verilog HDL language development platform NC divider circuit design, the use of CNC dividing principles music playing hardware circuit design and customize LPM-ROM to store music data,
Platform: | Size: 1049600 | Author: 李永科 | Hits:

[OS program] Divider

Description: 用Verilog HDL语言实现分频器，初学，简单(The realization of frequency divider in Verilog HDL, Elementary learning is simple)
Platform: | Size: 103424 | Author: wmy36 | Hits:

[VHDL-FPGA-Verilog] frequency divider and testbench

Description: a frequency divider and test bench with simulation results
Platform: | Size: 493568 | Author: abitofhero | Hits:
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