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[Com Portpay500_20535

Description: 功能特点: 1.可采用十六进制发送和接收。 2.可对接收区里的数据进行字符和十六进制实时转换。 3.可对发送的命令保存起来,下次进入时自动加载。 4.内部固化了十个命令串。 5.对发送和接收的数据进行计数 6.可自动发送数据 -Features: 1. Can send and receive hexadecimal. 2. Can receive the data area hexadecimal characters and real-time conversion. 3. May be sent to preserve order, and automatically load the next round. 4. Internal curing ten command string. 5. To send and receive data count 6. Can automatically send data
Platform: | Size: 278528 | Author: usa2883 | Hits:

[Windows Developcounter24

Description: 24进制计数,可以执行异步复位。该文件包含整个项目-24 hexadecimal counting, can perform asynchronous reset. This document contains the entire project
Platform: | Size: 180224 | Author: iyoung | Hits:

[VHDL-FPGA-Verilogclock

Description: 数字钟的程序,功能说明如下所示: 1.完成秒/分/时的依次显示并正确计数; 2.秒/分/时各段个位满10正确进位,秒/分能做到满60向前进位; 3.定时闹钟:实现整点报时,通过语音设备来实现具体的报时; 4.时间设置,也就是手动调时功能:当认为时钟不准确时,可以分别对分/时钟进行调整 5.可以选择使用12进制计时或者24进制计时。 使用QuartusII6.0编译仿真通过,语言使用的是VHDL,可以方便的移植到其他的平台上面。 -Digital clock procedures, functional description is as follows: 1. Completed sec/min/h and the sequence shows the correct count 2. Sec/min/h in the paragraphs of the correct 10-bit full binary, seconds/minutes to achieve the age of 60 to the forward position 3. regular alarm clock: realize the whole point of time, through the voice equipment to realize specific time 4. time settings, which is manually adjusted when the function: When the clock does not consider accurate, they can respectively sub/clock adjust 5. can choose to use 12 or 24 hexadecimal hexadecimal time time. QuartusII6.0 simulation through the use of compiler, language used is VHDL, can be easily ported to other platforms above.
Platform: | Size: 232448 | Author: 余宾客 | Hits:

[Software Engineeringdianzishizhong

Description: 题目:电子时钟的设计 一、实验目的: 1. 掌握多位计数器相连的设计方法。 2. 掌握十进制、六十进制、二十四进制计数器的设计方法。 3. 继续巩固多位数码管的驱动及编码。 4. 掌握扬声器的驱动 5. 掌握EPLD技术的层次化设计方法 二、实验要求: 1.用时、分、秒计数显示功能,以24小时循环计时。 2.具用清零,调节小时、分钟功能。 3.具用整点报时功能。 -Title: E-clock design, experimental purposes: 1. To master a number of counters connected to the design method. 2. Grasp the metric system, six decimal, hexadecimal 24 counter design. 3. Continue to consolidate a number of digital tube drivers and coding. 4. Grasp the speaker driver 5. EPLD technology to master-level design method II, the experimental requirements: 1. With hours, minutes and seconds count display to a 24-hour cycle time. 2. With a zero, adjust hours, minutes functions. 3. The whole point of using a time function.
Platform: | Size: 167936 | Author: li | Hits:

[VHDL-FPGA-Verilogwork5FREQTEST

Description: 8位十六进制频率计设计 根据频率的定义和频率测量的基本原理,测定信号的频率必须有一个脉宽为1s的输入信号脉冲计数允许信号;1s计数结束后,计数值被锁入锁存器,计数器清零,为下一测频计数周期做好准备。测频控制信号可由一个独立的发生器(FTCTRL)来产生。-8-bit hexadecimal Cymometer designed in accordance with the definition of frequency and frequency of the basic principles of measurement to determine the frequency of the signal must have a pulse width of the input signal for 1s permit pulse counting signal 1s counting after the total value was locked into the lock depositors, counters cleared for the next count cycle frequency measurement ready. Frequency control signal generator may be an independent (FTCTRL) to generate.
Platform: | Size: 244736 | Author: lkiwood | Hits:

[Windows Developmenglongyu30

Description: 模为12计数器 时钟电路需用到,能实现12进制的计数-Counter mode clock circuit 12 may need to rely on, to achieve a count of 12 hexadecimal
Platform: | Size: 16384 | Author: 王雨 | Hits:

[VHDL-FPGA-Verilogtimer

Description: 能够实现小时(24进制)、分钟和秒钟(60进制)的计数功能 具有复位功能 功能扩展:具有整点报时提示、定时闹钟等功能 -To achieve an hour (24 hexadecimal), minutes and seconds (60 hexadecimal) count function function reset function expansion: with the whole point timekeeping tips, regular features such as alarm clock
Platform: | Size: 663552 | Author: doraemon | Hits:

[assembly languagexunhuan

Description: (1)编写分支结构.asm文件实现: 键盘输入以‘$’为结束符的长度不超过80的字符串(含字母、数字、其他字符),对其中的非数字字符计数。统计结果用十六进制数屏幕显示。 (2)编写分支结构.asm文件实现: 定义一串以‘$’结束的字符串,给每一个字符均加上偶校验位。统计有多少个字符因含有奇数个1而加上了校验位,结果存入N单元。 -(1) the preparation of branch structure. Asm file to achieve: keyboard input in $ to end at the length of not more than 80 strings (including letters, numbers, other characters), of which non-numeric character count. Statistical results with a few hexadecimal display. (2) the preparation of branch structure. Asm file to achieve: the definition of a string with $ end of string to each of the characters are combined with dual parity bit. Statistics because of the number of characters containing odd-numbered months 1 and added a parity bit, the result deposited in N units.
Platform: | Size: 36864 | Author: 李平 | Hits:

[Windows Develop1

Description: 问题描述: 一本书的页码从自然数1 开始顺序编码直到自然数n。书的页码按照通常的习惯编排,每个页码都不含多余的前导数字0。例如,第6 页用数字6 表示,而不是06 或006 等。数字计数问题要求对给定书的总页码n,计算出书的全部页码中分别用到多少次数字0,1,2,…,9。 编程任务: 给定表示书的总页码的10 进制整数n (-Description of the problem: the page of a book from the natural number 1 until the beginning of coding sequence of natural number n. Book in accordance with the usual habits of page layout, each page are the leading non-redundant number of 0. For example, on page 6 with the number 6 that, rather than 06 or 006 and so on. Count the number of problem calls for a given book' s total page number n, to calculate the total number of books used, respectively, the number of times the number 0,1,2, ..., 9. Programming tasks: Given that the book' s total page 10 hexadecimal integer n (
Platform: | Size: 1024 | Author: yuecuiping | Hits:

[matlabcounter16

Description: 利用simulink制作的十六进制计数器-Simulink produced using hexadecimal counter
Platform: | Size: 7168 | Author: 程诗宇 | Hits:

[SCMshumaxianshi

Description: 系统上电后会有提示音,并且数码管显示0。K1键使数码管进行十六进制减1计数显示,K2键使数码管进行十六进制加1计数显示。数码管显示的同时,发光两极管将显示对应的二进制数。亮表示1,灭表示0-Power system will be prompted after the tone and digital display 0. K1 key for digital control by a count of hexadecimal display, K2 keys for digital control plus 1 count hexadecimal display. At the same time, digital tube display, light emitting polarized tube will show the corresponding binary number. Liang said that 1, to eliminate that 0
Platform: | Size: 18432 | Author: sunbin | Hits:

[VHDL-FPGA-VerilogCOUNT

Description: 这是一个十六进制的加减计数器源代码,把其修改一下就可以用其他进制了-This is a hexadecimal addition and subtraction counter source code, its change it can use other hex of the
Platform: | Size: 283648 | Author: max | Hits:

[Algorithmb4-1.8

Description: 大数相乘基本算法,相当于模拟手算。使用GMP生成指定数位的01串大数,将生成的01串用char型截取,运算中其实是以一次取4位进行运算。相当于16进制运算。-Multiplication of large numbers of basic algorithms, equivalent to simulate hand count. GMP is generated using the specified digit string of 01 large numbers, will generate a 01 string with the char-type interception operations are actually carried out is a time to take four operations. Is equivalent to 16 hexadecimal operations.
Platform: | Size: 3072 | Author: Ivy | Hits:

[SCMjianyishuzizhong

Description: 一个简易的数字钟,能显示小时、分和秒,是一台按秒计数并显示的计时器,其中秒和分为60进制,小时为24进制计数。-A simple digital clock showing the hours, minutes and seconds, is one count per second and displays the timer, which is divided into 60 seconds, and decimal, hexadecimal count for 24 hours.
Platform: | Size: 10240 | Author: 刘逊 | Hits:

[VHDL-FPGA-VerilogDF2C8_03_NixeTube

Description: :8 个数码管从 0 开始计数,每次增加 1;每位显示的字符包括从 “0~F”16 个十六进制数;  按下复位按键之后,计数从 0 重新开始。由此可验证数码管、有 源时钟和复位按键等功能。-: 8 digital tube starts counting from 0, for each increase of 1 each displayed character from " 0 ~ F" 16 hexadecimal numbers press the reset button, the count start from 0. Thus verifiable digital control, active functions such as clock and reset button.
Platform: | Size: 732160 | Author: qiutian | Hits:

[SCMled

Description: AT89C2051驱动6位共阴LED管 并将计数65535 每位扫1ms,定时0, 加了码表0-9,其中p1.7\a,,,,,p1.0\h 50h,,,54h,个,十,百,千,万 40h十六进制低位,41十六进制高位-AT89C2051 drive common cathode LED Tube 6 6 AT89C2051 common cathode LED driver tube and count 65535 each sweep 1ms, time 0 added a code table 0-9, which p1.7 \ a ,,,,, p1.0 \ h 50h,,, 54h, one, ten, hundred, thousand, million 40h hex low, 41 high in hexadecimal
Platform: | Size: 1024 | Author: ZHAO | Hits:

[Internet-NetworkSocketTest

Description: 实现Client Socket及其SeverSocket,实现启动 停止 16进制发送,发送计数 传输速率等-implement Client Socket and SeverSocket, to implement start, stop ,sending hexadecimal, send count, transmission rate
Platform: | Size: 132096 | Author: 毛继科 | Hits:

[VHDL-FPGA-Verilogcnt16anddisplay

Description: 源代码实现十六进制的显示,包括三个模块:分频、计数、显示。适合vhdl的初级读者以及在校大学生-Source code in hexadecimal display, consists of three modules: frequency, count, display. Vhdl for primary readers and college students
Platform: | Size: 4096 | Author: 刘海亮 | Hits:

[SCMsy1(1)

Description: 每按一次按键,累计按键次数并通过LED显示出来,且采用16进制计数。-Each time you press the button, the cumulative number of keystrokes and through the LED display and hexadecimal count.
Platform: | Size: 15360 | Author: 钟建新 | Hits:

[VHDL-FPGA-Verilogdianzhen

Description: 需要实现点阵按列依次并且循环显示的效果,可以分析视觉上可以观察到列的变化,则列的扫描频率必定要远远小于行扫描的频率。在程序中,设置行扫描的频率等于前次实验中数码管扫描的频率,设置列扫描的频率为5HZ,即每0.2s显示亮的一列向前推进一列。在程序中,使用16进制计数作为74HC154的输入:分出5hz的频率,并用其计数,将计数值作为74HC154,则其译码产生的输出变化也为5hz,并且实现每列一次选通。由于每行对应的数码管共阳极。直接赋高电平。则可以实现所需要的功能。行扫面则是要实现先依行点亮,再实现列点亮。-Lattice scanning procedures: need to achieve in sequence and cycle according to the dot matrix display effect, can be analyzed visually observed column changes, the scanning frequency of the column must be far less than the line scanning frequency. In the program, set the line scan frequency is equal to the previous experiment in digital scanning frequency, set the column scanning the frequency is 5HZ, each 0.2S display a list of bright forward. In the program, using 16 hexadecimal count as the input of 74HC154: the frequency of 5Hz, and the count, the count of the 74HC154 output, change its decoding generated for the 5Hz, and the realization of each column of a selected through the digital tube. Because each row corresponding to the anode. The high level can be directly assigned. To achieve the required functionality. For scanning is to achieve the first in line to realize the column light, lit. This program is based on the Quartus programming environment, using Veilog language Langu
Platform: | Size: 728064 | Author: 丁明凯 | Hits:
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