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[Other resource] DesignofVeryDeepPipelinedMultipliersforFPGAs(IEEE)

Description: 关于FPGA流水线设计的论文 This work investigates the use of very deep pipelines for implementing circuits in FPGAs, where each pipeline stage is limited to a single FPGA logic element (LE). The architecture and VHDL design of a parameterized integer array multiplier is presented and also an IEEE 754 compliant 32-bit floating-point multiplier. We show how to write VHDL cells that implement such approach, and how the array multiplier architecture was adapted. Synthesis and simulation were performed for Altera Apex20KE devices, although the VHDL code should be portable to other devices. For this family, a 16 bit integer multiplier achieves a frequency of 266MHz, while the floating point unit reaches 235MHz, performing 235 MFLOPS in an FPGA. Additional cells are inserted to synchronize data, what imposes significant area penalties. This and other considerations to apply the technique in real designs are also addressed.
Platform: | Size: 179551 | Author: 李中伟 | Hits:

[Other] IEEE754Floatingpoint

Description: IEEE 754 Floating point
Platform: | Size: 57643 | Author: whr | Hits:

[WEB Code] IEEE_754

Description: IEEE 754 浮点数的表示精度探讨.doc
Platform: | Size: 29307 | Author: liu | Hits:

[Windows Develop] VFloat_lib_Nov14_2007

Description: 遵循 IEEE 754 标准的浮点运算 库 内含 denorm norm fp_add/sub fp_mult fp_devision 可以快速模拟单双精度浮点运算 导师授权使用
Platform: | Size: 64885 | Author: david | Hits:

[Documents] float-ieee754

Description: floating point number presentation(IEEE 754 standard)
Platform: | Size: 37888 | Author: dvd | Hits:

[Other] DesignofVeryDeepPipelinedMultipliersforFPGAs(IEEE)

Description: 关于FPGA流水线设计的论文 This work investigates the use of very deep pipelines for implementing circuits in FPGAs, where each pipeline stage is limited to a single FPGA logic element (LE). The architecture and VHDL design of a parameterized integer array multiplier is presented and also an IEEE 754 compliant 32-bit floating-point multiplier. We show how to write VHDL cells that implement such approach, and how the array multiplier architecture was adapted. Synthesis and simulation were performed for Altera Apex20KE devices, although the VHDL code should be portable to other devices. For this family, a 16 bit integer multiplier achieves a frequency of 266MHz, while the floating point unit reaches 235MHz, performing 235 MFLOPS in an FPGA. Additional cells are inserted to synchronize data, what imposes significant area penalties. This and other considerations to apply the technique in real designs are also addressed.-FPGA pipelined designs on paper This work investigates the use of very deep pipelines forimplementing circuits in FPGAs, where each pipelinestage is limited to a single FPGA logic element (LE). Thearchitecture and VHDL design of a parameterized integerarray multiplier is presented and also an IEEE 754compliant 32-bit floating-point multiplier. We show how towrite VHDL cells that implement such approach, and howthe array multiplier architecture was adapted. Synthesisand simulation were performed for Altera Apex20KEdevices, although the VHDL code should be portable toother devices. For this family, a 16 bit integer multiplierachieves a frequency of 266MHz, while the floating pointunit reaches 235MHz, performing 235 MFLOPS in anFPGA. Additional cells are inserted to synchronize data, what imposes significant area penalties. This and otherconsiderations to apply the technique in real designs arealso addressed.
Platform: | Size: 179200 | Author: 李中伟 | Hits:

[Other] IEEE754Floatingpoint

Description: IEEE 754 Floating point
Platform: | Size: 57344 | Author: | Hits:

[File Format] IEEEtran

Description: ieee投稿latex模板，包括会议期刊等-latex template ieee Contributors, including the periodicals
Platform: | Size: 688128 | Author: wangqiang | Hits:

[Documents] IEEE_754

Description: IEEE 754 浮点数的表示精度探讨.doc-IEEE 754 floating-point to explore the accuracy of that. Doc
Platform: | Size: 28672 | Author: liu | Hits:

[Windows Develop] VFloat_lib_Nov14_2007

Description: 遵循 IEEE 754 标准的浮点运算 库 内含 denorm norm fp_add/sub fp_mult fp_devision 可以快速模拟单双精度浮点运算 导师授权使用 -Follow the IEEE 754 standard floating point library includes denorm norm fp_add/sub fp_mult fp_devision can quickly simulate single-and double-precision floating-point operations instructors are authorized to use
Platform: | Size: 64512 | Author: david | Hits:

[CSharp] IEEE754Convertor

Description: 按照IEEE 754标准对Float和Double类型进行转换-In accordance with the IEEE 754 standard types of Float and Double conversion
Platform: | Size: 749568 | Author: bragi | Hits:

[VHDL-FPGA-Verilog] add(FLP)

Description: 一个32位元的浮点数加法器，可将两IEEE 754格式内的值进行相加-A 32-bit floating-point adder can be both within the IEEE 754 format to add value
Platform: | Size: 10240 | Author: TTJ | Hits:

[VHDL-FPGA-Verilog] mul(FLP)

Description: 一个32位元的浮点数乘法器，可将两IEEE 754格式的值进行相乘-A 32-bit floating-point multipliers, can be two format IEEE 754 values multiplied
Platform: | Size: 2048 | Author: TTJ | Hits:

[Program doc] IEEE_754

Description: IEEE STD 754 的格式说明和算法的C语言实现-IEEE STD 754 and the format of the C language algorithm
Platform: | Size: 55296 | Author: sr0303 | Hits:

[Other] IEEE754

Description: ieee754的标准，原英文版的！Twenty years ago anarchy threatened floating-point arithmetic. Over a dozen commercially significant arithmetics boasted diverse wordsizes, precisions, rounding procedures and over/underflow behaviors, and more were in the works. “Portable” software intended to reconcile that numerical diversity had become unbearably costly to develop. Thirteen years ago, when IEEE 754 became official, major microprocessor manufacturers had already adopted it despite the challenge it posed to implementors. With unprecedented altruism, hardware designers had risen to its challenge in the belief that they would ease and encourage a vast burgeoning of numerical software. They did succeed to a considerable extent. Anyway, rounding anomalies that preoccupied all of us in the 1970s afflict only CRAY X-MPs — J90s now.-ieee754 standards, the original English version of the! Twenty years ago anarchy threatened floating-point arithmetic. Over a dozen commercially significant arithmetics boasted diverse wordsizes, precisions, rounding procedures and over/underflow behaviors, and more were in the works. " Portable" software intended to reconcile that numerical diversity had become unbearably costly to develop. Thirteen years ago, when IEEE 754 became official, major microprocessor manufacturers had already adopted it despite the challenge it posed to implementors. With unprecedented altruism, hardware designers had risen to its challenge in the belief that they would ease and encourage a vast burgeoning of numerical software. They did succeed to a considerable extent. Anyway, rounding anomalies that preoccupied all of us in the 1970s afflict only CRAY X-MPs- J90s now.
Platform: | Size: 99328 | Author: wangdiao | Hits:

[Windows Develop] IEEE754

Description: 依據IEEE-754 浮點數標準，將32 bit的Hex,轉換為浮點數-From 32-bit Hexadecimal Representation To Decimal Floating-Point for the IEEE-754 floating-point standard
Platform: | Size: 35840 | Author: lan_chia_fan | Hits:

[Other] IEEE-754

Description: IEEE 754 对十六进制数的 解析 可以显示 二进制 以及 正负等-IEEE 754 hexadecimal number parsing
Platform: | Size: 7168 | Author: soul | Hits:

[VHDL-FPGA-Verilog] 6.An-FPGA-Based-High-Speed-IEEE-754-Double-Precis

Description: An FPGA Based High Speed IEEE-754 Double Precision Floating Point Multiplier
Platform: | Size: 786432 | Author: chuba | Hits:

[Program doc] IEEE-754-Floating-point

Description: IEEE 754 浮点数转换标准-IEEE 754 Floating point
Platform: | Size: 57344 | Author: op0707 | Hits:

[Other] IEEE-754

Description: 从项目中提取的功能函数，主要是把IEEE 754的浮点数与16进制进行互相转化。文件只提供了函数，需使用者自己重新添加一些头文件进行配置。目前功能的正确性在项目运行过程得到了验证，可以放心使用。代码里有注释。-Float IEEE754 transform to byte
Platform: | Size: 2048 | Author: tidavery | Hits:
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