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[VHDL-FPGA-Verilog] ad9777的测试程序，对SPI进行初始化，运用ISE环境，成功地进行综合和实现.rar

Description: ad9777的测试程序，对SPI进行初始化，运用ISE环境，成功地进行综合和实现
Platform: | Size: 2664973 | Author: Ariesl | Hits:

[Technology Management] verilog与ISE

Description: verilog与ISE系列的，非常好
Platform: | Size: 7246820 | Author: win_hshiw | Hits:

[VHDL-FPGA-Verilog] VerilogHDLPLI

Description: Verilog HDL的PLI子程序接口，用于与用户C程序在2个方向上传输数据，可用xilinx ISE，quartusii或modelsim仿真，-Verilog HDL PLI subroutine interfaces, for C program with the user in the direction of two transmission of data, available xilinx ISE. quartusii or modelsim simulation,
Platform: | Size: 1024 | Author: 杨锐 | Hits:

[Other Embeded program] yunsuan-verilog

Description: 运算器的实现，即实验指导书中的实验一，文件中包含有原代码及端口设置（可变），用vrilog HDL编程，Xilinx ISE 6仿真，并在实际电路中得到实现．-operations for the realization of the experimental guidance of a book. document contains the original code and port settings (variable), with vrilog HDL programming, Xilinx ISE 6 simulation, and the actual circuit realization.
Platform: | Size: 1600512 | Author: 王越 | Hits:

[Other Embeded program] trafficLight-verilog

Description: 交通灯状态机的实现，用verilog HDL编程，Xilinx ISE 6仿真，在实际电路中得到验证．-traffic lights to achieve the state machine, with verilog HDL programming, Xilinx ISE 6 simulation, the actual circuit have been tested.
Platform: | Size: 1532928 | Author: 王越 | Hits:

[VHDL-FPGA-Verilog] AD9229-FPGA-files

Description: adi串行AD AD9229的控制使用ISE平台 Verilog语言 -adi serial ADAD9229 control the use of ISE platform Verilog language
Platform: | Size: 184320 | Author: 徐凯 | Hits:

[VHDL-FPGA-Verilog] VGADIY

Description: 自己编的VGA彩条信号发生器verilog ise环境-Own the VGA color signal generator verilog ise Environment
Platform: | Size: 416768 | Author: mcuxxq | Hits:

[VHDL-FPGA-Verilog] ADC_INTERFACE

Description: it is a verilog code written for MAX1886 ADC interin modelsim simulator and it will synthesize in xinlix ise 8.2i.i have tested it om my kit. -it is a verilog code written for MAX1886 ADC interin modelsim simulator and it will synthesize in xinlix ise 8.2i.i have tested it om my kit.
Platform: | Size: 6144 | Author: yasir ateeq | Hits:

[Communication-Mobile] D_BLAST44

Description: MIMO 4*4系统D-BLAST编译码方案，利用ISE仿真环境，verilog编程实现。-MIMO 4* 4 system codec D-BLAST program, using ISE simulation environment, verilog programming implementation.
Platform: | Size: 303104 | Author: 黄虎 | Hits:

[VHDL-FPGA-Verilog] iic

Description: 一个verilog源代码，可用ISE等实现，功能为I2C接口标准建模。-A verilog source code, can be used, such as the realization of ISE, the functional model for the I2C interface standard.
Platform: | Size: 306176 | Author: PUDN_CHEN | Hits:

[Other] sdram

Description: 在ISE开发环境下的单速率SDRAM简单读写控制器设计，用的是verilog硬件描述语言-ISE development environment in a single-rate SDRAM controller read and write simple design, using the verilog hardware description language
Platform: | Size: 157696 | Author: 小桂 | Hits:

[matlab] wierlesscommunicationfpgadesignmatlabverilogcode.r

Description: 无线通信FPGA设计的所有源码，具有良好的使用价值-verilog matlab ISE
Platform: | Size: 214016 | Author: 吕鑫宇 | Hits:

[Embeded-SCM Develop] I2C

Description: Verilog实现的I2C协议，直接在ISE下打开就可以-Verilog implementation I2C protocol to open directly in the ISE can be
Platform: | Size: 212992 | Author: Roy | Hits:

[Com Port] UART

Description: Verilog实现的UART程序，用ISE打开工程文件即可-Verilog implementation UART program, open the project file with the ISE can be
Platform: | Size: 22528 | Author: Roy | Hits:

[VHDL-FPGA-Verilog] USB

Description: Verilog实现的USB程序，用ISE打开工程文件即可-Verilog implementation USB program, open the project file with the ISE can be
Platform: | Size: 140288 | Author: Roy | Hits:

[VHDL-FPGA-Verilog] Multiplier

Description: It s a design of a 4*4 multiplier based on Verilog, using Xilinx ISE.
Platform: | Size: 859136 | Author: wayne | Hits:

[Embeded-SCM Develop] I2C

Description: 用verilog编写实现的I2C协议源码，自带控制台，解压后用ISE打开工程文件即可。-Prepared achieved with the I2C protocol verilog source code, comes with the console, after decompression project file can be opened with the ISE.
Platform: | Size: 244736 | Author: 陈阳 | Hits:

[VHDL-FPGA-Verilog] canbus

Description: 用verilog编写实现的CAN总线控制器源码，自带testbench，解压后用ISE打开工程文件即可。-Prepared with the verilog source code to achieve the CAN bus controller, bring their own testbench, after decompression project file can be opened with the ISE.
Platform: | Size: 1079296 | Author: 陈阳 | Hits:

[VHDL-FPGA-Verilog] Kaifang

Description: 利用ISE编写的实现开方功能的verilog程序，利用了CORDICIP核，可以完成开方功能-Prepared using ISE verilog program to achieve prescribing functions, using the CORDICIP nuclear, prescribing functions to be completed
Platform: | Size: 421888 | Author: 蜡笔 | Hits:

[VHDL-FPGA-Verilog] Verilog-Design

Description: 包括三个文档: 1.基于Altera Quartus II 的模块化设计应用 2.基于Xilinx ISE的的模块化设计示例 3.模块化设计方法的设计流程-Consists of three documents: 1. Based on Altera Quartus II modular design applications 2. Xilinx ISE based on the modular design of Example 3. Modular Design for design process
Platform: | Size: 252928 | Author: Joseph | Hits:
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