Description: A verilog source code, can be used, such as the realization of ISE, the functional model for the I2C interface standard.
- [IICforsopcbuilder] - IIC controller for Sopc Builder
- [iic_vhdl] - IIC bus controller VHDL realize- VHDL So
- [SPI_IIC_design_example] - ALTERA provided the original routine, it
- [sdram] - ISE development environment in a single-
- [DES] - In the ISE platform, using Verilog progr
File list (Check if you may need any files):
iic
...\ISE
...\...\iic
...\...\...\.untf
...\...\...\automake.log
...\...\...\bitgen.ut
...\...\...\coregen.log
...\...\...\coregen.prj
...\...\...\i2c.bgn
...\...\...\i2c.bit
...\...\...\i2c.bld
...\...\...\i2c.cmd_log
...\...\...\i2c.drc
...\...\...\i2c.lfp
...\...\...\i2c.lso
...\...\...\i2c.mrp
...\...\...\i2c.nc1
...\...\...\i2c.ncd
...\...\...\i2c.ngc
...\...\...\i2c.ngd
...\...\...\i2c.ngm
...\...\...\i2c.ngr
...\...\...\i2c.pad
...\...\...\i2c.pad_txt
...\...\...\i2c.par
...\...\...\i2c.pcf
...\...\...\i2c.placed_ncd_tracker
...\...\...\i2c.prj
...\...\...\i2c.routed_ncd_tracker
...\...\...\i2c.stx
...\...\...\i2c.syr
...\...\...\i2c.twr
...\...\...\i2c.twx
...\...\...\i2c.ucf
...\...\...\i2c.ucf.untf
...\...\...\i2c.ut
...\...\...\i2c.v
...\...\...\i2c.xpi
...\...\...\i2c_clk.v
...\...\...\i2c_last_par.ncd
...\...\...\i2c_map.ncd
...\...\...\i2c_map.ngm
...\...\...\i2c_pad.csv
...\...\...\i2c_pad.txt
...\...\...\i2c_st.v
...\...\...\i2c_vhdl.prj
...\...\...\iic.dhp
...\...\...\iic.npl
...\...\...\xst
...\...\...\...\work
...\...\...\...\....\hdllib.ref
...\...\...\...\....\vlg1E
...\...\...\...\....\.....\i2c.bin
...\...\...\...\....\vlg20
...\...\...\...\....\.....\i2c_st.bin
...\...\...\...\....\vlg53
...\...\...\...\....\.....\i2c_clk.bin
...\...\...\_impact.cmd
...\...\...\_impact.log
...\...\...\_ngo
...\...\...\....\netlist.lst
...\...\...\__projnav
...\...\...\.........\bitgen.rsp
...\...\...\.........\coregen.rsp
...\...\...\.........\ednTOngd_tcl.rsp
...\...\...\.........\i2c.xst
...\...\...\.........\i2c_ncdTOut_tcl.rsp
...\...\...\.........\iic.gfl
...\...\...\.........\iic_flowplus.gfl
...\...\...\.........\map.log
...\...\...\.........\nc1TOncd_tcl.rsp
...\...\...\.........\par.log
...\...\...\.........\parentAssignPackagePinsApp_tcl.rsp
...\...\...\.........\posttrc.log
...\...\...\.........\runXst_tcl.rsp
...\...\...\__projnav.log
...\RTL
...\...\BACK
...\...\....\clk_rst.v
...\...\....\i2c.v
...\...\....\i2c_clk.v
...\...\....\i2c_rreg.v
...\...\....\i2c_st.v
...\...\....\i2c_tbuf.v
...\...\....\i2c_wreg.v
...\...\i2c.v
...\...\i2c_clk.v
...\...\i2c_st.v
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