Description: ALTERA provided the original routine, it is difficult to find online and in the MAX2 series chip-off, VHDL and VERILOG two languages
- [I2CbuscontrollerprovidesALTERA-VHDL] - I2C Bus Controller ALTERA the VHDL sourc
- [sc] - Prepared using Verilog table tennis game
- [rong] - IIC bus is a code, a VGA display text co
- [iic_vhdl] - IIC bus controller VHDL realize- VHDL So
- [IIC-CPLD] - IIC bus protocol ~ IIC bus communication
- [pwm_source] - Altera in the official line on the SOPC
- [iic] - A verilog source code, can be used, such
- [IICVHDL] - NO
- [iic] - Cpld single-chip computer and communicat
File list (Check if you may need any files):
AN486_SPI_to_I2C_Altera_MAX_II_CPLD_Design_Example
..................................................\code
..................................................\....\SPI_to_I2C.v
..................................................\modelsim
..................................................\........\SPI_to_I2C.cr.mti
..................................................\........\SPI_to_I2C.mpf
..................................................\........\SPI_to_I2C.v
..................................................\........\SPI_to_I2C_test.v
..................................................\........\SPI_to_I2C_test.v.bak
..................................................\........\transcript
..................................................\........\vsim.wlf
..................................................\........\wave.do
..................................................\........\work
..................................................\........\....\@i2@c_master
..................................................\........\....\............\verilog.psm
..................................................\........\....\............\_primary.dat
..................................................\........\....\............\_primary.vhd
..................................................\........\....\@s@p@i_slave
..................................................\........\....\............\verilog.psm
..................................................\........\....\............\_primary.dat
..................................................\........\....\............\_primary.vhd
..................................................\........\....\@s@p@i_to_@i2@c
..................................................\........\....\...............\verilog.psm
..................................................\........\....\...............\_primary.dat
..................................................\........\....\...............\_primary.vhd
..................................................\........\....\@s@p@i_to_@i2@c_test
..................................................\........\....\....................\verilog.psm
..................................................\........\....\....................\_primary.dat
..................................................\........\....\....................\_primary.vhd
..................................................\........\....\divider
..................................................\........\....\.......\verilog.psm
..................................................\........\....\.......\_primary.dat
..................................................\........\....\.......\_primary.vhd
..................................................\........\....\internal_oss_altufm_osc_7p3
..................................................\........\....\...........................\verilog.psm
..................................................\........\....\...........................\_primary.dat
..................................................\........\....\...........................\_primary.vhd
..................................................\........\....\_info
..................................................\quartus
..................................................\.......\db
..................................................\.......\..\SPI_to_I2C.asm.qmsg
..................................................\.......\..\SPI_to_I2C.asm_labs.ddb
..................................................\.......\..\SPI_to_I2C.cbx.xml
..................................................\.......\..\SPI_to_I2C.cmp.cdb
..................................................\.......\..\SPI_to_I2C.cmp.hdb
..................................................\.......\..\SPI_to_I2C.cmp.logdb
..................................................\.......\..\SPI_to_I2C.cmp.rdb
..................................................\.......\..\SPI_to_I2C.cmp.tdb
..................................................\.......\..\SPI_to_I2C.cmp0.ddb
..................................................\.......\..\SPI_to_I2C.dbp
.........
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