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[Other resource] ldpc

Description: 关于LDPC编码的MATLAB实现仿镇,求关于LDPC码的FPGA实现-LDPC coding on the fake MATLAB town, seeking LDPC on the FPGA
Platform: | Size: 20799 | Author: ngy68 | Hits:

[matlab] ldpc

Description: 关于LDPC编码的MATLAB实现仿镇,求关于LDPC码的FPGA实现-LDPC coding on the fake MATLAB town, seeking LDPC on the FPGA
Platform: | Size: 20480 | Author: | Hits:

[Streaming Mpeg4] ddd

Description: DVB—S2中LDPC码编码器的FPGA设计与实现-DVB-S2 in the LDPC code encoder FPGA Design and Implementation
Platform: | Size: 244736 | Author: sss | Hits:

[Streaming Mpeg4] ldpc_encoder_802_3an.v

Description: LDPC 编码的Verilog源代码，我没有验证，不知道效果如何，与大家分享，供大家参考。-LDPC-coded Verilog source code, I did not verify, I do not know how to share with you, for your reference.
Platform: | Size: 622592 | Author: peter | Hits:

[Software Engineering] ldpc1

Description: LDPC编码的研究与硬件实现 是关于LDPC码的一篇很好的文章-LDPC coding research and hardware implementation of LDPC codes on a very good article
Platform: | Size: 4176896 | Author: 韩杨 | Hits:

[Communication] ldpc7_3

Description: the attached file consists of LDPC code (7,3). this code can be easily implemented on fpga kit(sparten-3)
Platform: | Size: 2048 | Author: babi | Hits:

[Program doc] CMMB_LDPC

Description: 一篇关于CMMB中LDPC编码译码的论文，解释得很详细，还有硬件(FPGA)实现方法-CMMB in an article on decoding LDPC coded paper to explain it in detail, as well as the hardware (FPGA) Implementation Method
Platform: | Size: 6098944 | Author: 王家祥 | Hits:

[Program doc] DVB_S2_LDPC_implementation

Description:
Platform: | Size: 4829184 | Author: 梅国强 | Hits:

[VHDL-FPGA-Verilog] ThedesignofLDPCEncodeasedonFieldProgrammGateArry.r

Description: In this paper, we introduce the priplince of the LDPC Encode. And introduce how to realize the LDPC encode based on the FPGA.-The design of LDPC Encode based on Field Programm Gate Arry
Platform: | Size: 612352 | Author: SEU | Hits:

[VHDL-FPGA-Verilog] Realization_of_FPGA_for_LDPC_encoding

Description: 低密度奇偶校验码(简称LDPC码)是目前距离香农限最近的一种线性纠错码，它的直接编码运算量较大，通常具有码长的二次方复杂度．为此，利用有效的校验矩阵，来降低编码的复杂度，同时研究利用大规模集成电路实现LDPC码的编码．在ISE 8．2软件平台上采用基于FPGA的Verilog HDL语言实现了有效的编码过程，为LDPC码的硬件实现和实际应用提供了依据-Abstract：Low．density parity·check code(LDPC code)is a kind of linear eror·correcting code nearest to Shannon Limit．For LDPC cod e，the computational overhead for direct encoding operations is large，as the complexity of encod ing is the square of the length of codeword．Hence，this paper reduces the complexity of coding by using effective parity—check matrix，and realizes the encoding device for LDPC code by use of large·scale integrated circuits．The effective encoding process based on FPGA with Verilog HDL language is implemented on ISE 8．2 software platform ，providing a feasible basis for hardware implementation an d practical application of LDPC code．
Platform: | Size: 165888 | Author: 秦小星 | Hits:

[Technology Management] LDPC

Description: 日本人关于量子密钥发送方法专利，没有被批准，此类专利国内还没有出现-Japanese patent on the method of quantum key transmission, has not been approved, such patents country has not yet appeared
Platform: | Size: 4936704 | Author: yuanlei | Hits:

[VHDL-FPGA-Verilog] FPGA-LDPC

Description: 用FPGA实现使用LDPC编码器和译码器-FPGA implementation by using LDPC encoder and decoder
Platform: | Size: 484352 | Author: 雷锋 | Hits:

[VHDL-FPGA-Verilog] FPGA-for-LDPC-encoding

Description: LDPC Encoding Ebook Tetourial
Platform: | Size: 166912 | Author: moha | Hits:

[VHDL-FPGA-Verilog] ldpc-for-fpga-decoding

Description: ldpc译码算法的matlab实现，码长960，码率1/2,完全模拟fpga硬件实现语言，量化处理。-ldpc decoding using matalb,code length 960,code rate 1/2
Platform: | Size: 19456 | Author: shao | Hits:

[VHDL-FPGA-Verilog] the-decoding-algorithm-of-ldpc

Description: ldpc译码算法介绍及fpga verilog系统方案设计，包括log_bp算法、min_sum算法、scaling_min_sum算法等-introducing the ldpc code decoding algorithm and the related system design，including the log_bp,the min_sum and the scaling_min_sum
Platform: | Size: 81920 | Author: 类春阳 | Hits:

[Program doc] Design-of-LDPC-codes-on-FPGA

Description: 小论文《基于FPGA的（3,6）LDPC码并行译码器设计与实现》实现了码率为1/2，帧长为1008bits的规则（3,6）LDPC码译码器-Design and Implementation of Parallel Architectures Decoder for（3,6）LDPC Codes Based on FPGA code rate of 1/2 and block length of 1008 bits has been implemented based on FPGA(StatixⅡ-EP2S30F484C3) of Altera
Platform: | Size: 185344 | Author: CBang | Hits:

[Program doc] eIRA-LDPC-Codes-on-FPGA

Description: ＬＤＰＣ码的ＦＰＧＡ实现论文，外文ＩＥＥＥ文章，很有用的文献-FPGA implementation of LDPC codes Papers, Foreign IEEE article useful literature
Platform: | Size: 183296 | Author: 周健 | Hits:

[Software Engineering] ldpc

Description: 低密度校验码 ，很好用的代码，功能已经实现编码和译码-fpga ldpc
Platform: | Size: 64512 | Author: 537 | Hits:

[Software Engineering] QC_LDPC_FPGA

Description: LDPC QC-LDPC 基于FPGA的QC-LDPC实现 论文-LDPC QC-LDPC FPGA-based QC-LDPC detailed implementation steps Thesis
Platform: | Size: 1047552 | Author: chenghuachao | Hits:

[VHDL-FPGA-Verilog] LDPC码编译码算法的研究与实现_陈石平

Description: 本文首先回顾了LDPC码的发展历程和现状，介绍了LDPC码检验矩阵的构造、编 译码原理。在对编译码作了深入探讨和分析后，接着进行了RU算法编码和长码编码 的FPGA实现;根据二叉树的性质，提出了一种长码编码的ASIC优化设计的方法，节省 了大量硬件资源;论文详细阐述了CORDIC算法原理以及LDPC码译码中所采用的指 数函数和反双曲正切函数的FPGA实现:CORDIC内核及前后处理单元设计、仿真、综 合及数据分析，这对LDPC码的译码具有很重要的意义，为用数字VLSI来实现LDPC的 译码奠定了基础。同时在基于校验矩阵的环路检测定理基础上，将校验矩阵转化为转 移概率矩阵，详细分析并提出了一种基于转移概率矩阵的围长检测方法，并对其进行 了理论证明，具有很好的围长检测效果，以及状态分类判别。(Research and implementation of LDPC coding and decoding technology)
Platform: | Size: 1529856 | Author: 斯蓝蓝 | Hits:
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