Search - LOOKAHEAD ADDER

[WEB Code] ripple-lookahead-carryselect-adder

Description: Ripple Adder: 16-bit 全加,半加及ripple adder的设计及VHDL程序 Carry Look ahead Adder:4, 16, 32 bits 前置进位加法器的设计方案及VHDL程序 Carry Select Adder:16 Bits 进位选择加法器的设计方案及VHDL程序-Ripple Adder : 16-bit full adder, semi-Canada and the ripple adder design and VHDL procedures Carry Look ahead Adder : 4, 16, 32 bits front rounding Adder and the VHDL design procedures Carry Select Adder : 16 Bits Progressive Choice Adder design and VHDL - sequence
Platform: | Size: 15972 | Author: 李成 | Hits:

[Linux-Unix] cla_dc

Description: a demo script of \"carry lookahead adder\" for synopsys design compiler
Platform: | Size: 1906 | Author: heyong | Hits:

[Linux-Unix] cla_src

Description: carry lookahead adder verilog program
Platform: | Size: 1575 | Author: heyong | Hits:

[Documents] ripple-lookahead-carryselect-adder

Description: Ripple Adder: 16-bit 全加,半加及ripple adder的设计及VHDL程序 Carry Look ahead Adder:4, 16, 32 bits 前置进位加法器的设计方案及VHDL程序 Carry Select Adder:16 Bits 进位选择加法器的设计方案及VHDL程序-Ripple Adder : 16-bit full adder, semi-Canada and the ripple adder design and VHDL procedures Carry Look ahead Adder : 4, 16, 32 bits front rounding Adder and the VHDL design procedures Carry Select Adder : 16 Bits Progressive Choice Adder design and VHDL- sequence
Platform: | Size: 15360 | Author: 李成 | Hits:

[Linux-Unix] cla_dc

Description: a demo script of "carry lookahead adder" for synopsys design compiler
Platform: | Size: 2048 | Author: heyong | Hits:

[Linux-Unix] cla_src

Description: carry lookahead adder verilog program
Platform: | Size: 1024 | Author: heyong | Hits:

[Windows Develop] lookahead

Description: implement of carry look ahead adder vith verilog
Platform: | Size: 32768 | Author: shabnam | Hits:

[Other] adder

Description: 本设计是做了一个32位超前进位加法器，能够快速计算-This design is made of a 32-bit lookahead adder, to quickly calculate
Platform: | Size: 38912 | Author: zhaozimou | Hits:

[Algorithm] CLAA_32_BITS

Description: A 32-bit carry lookahead adder
Platform: | Size: 1024 | Author: yasser01 | Hits:

[VHDL-FPGA-Verilog] cla16

Description: 16位超前进位加法器的源代码，整个工程文件都有，是在ISE10.1下建立的，可以帮助理解超前进位原理（对了，是Verilog的，因为上面没看到只好选VHDL了）-16-bit look-ahead adder the source code files have the whole project was established under the ISE10.1 to help understand the lookahead principle (By the way, is the Verilog, because the election had not seen the top of the VHDL )
Platform: | Size: 644096 | Author: nikis | Hits:

[VHDL-FPGA-Verilog] VHDL-ripple-lookahead-carryselect-adder

Description: vhdl code for ripple carry adder, carry select adder and carry look ahead adder
Platform: | Size: 17408 | Author: praveen | Hits:

[VHDL-FPGA-Verilog] Lookahead-adder

Description: 超前进位加法器，可以实现提前实现进位，加速算法。-Lookahead adder
Platform: | Size: 23552 | Author: tom | Hits:

[VHDL-FPGA-Verilog] carry-lookahead-adder

Description: ddr 2 model by jaswant singh
Platform: | Size: 849920 | Author: jaswant singh | Hits:

[VHDL-FPGA-Verilog] adder

Description: 设计一个16×16位的流水线乘法器。乘法器部分采用16×16进位保留（Carry-save）阵列构成。最后一行部分积产生单元要求采用超前进位构成。 -Design of a 16 x 16 pipelined multiplier. Multiplier by 16 x 16 carry save array ( Carry-save ). The last line of the partial product generation unit requires use of carry lookahead.
Platform: | Size: 2048 | Author: raul | Hits:

[VHDL-FPGA-Verilog] lookahead-adder

Description: Quartus环境下的超前进位加法器的编写代码，适合初学数字逻辑设计的学习-Lookahead adder in Quartus
Platform: | Size: 295936 | Author: 陈轶博 | Hits:

[VHDL-FPGA-Verilog] ADDER

Description: 超前进位加法器。时序好，功能可靠.工程引用已经验证。-Lookahead adder. Timing is good, functional and reliable
Platform: | Size: 1024 | Author: 王建军 | Hits:

[Other] four-lookahead-adder

Description: verilog_HDL-四位超前进位加法器,学习资料，可以方便的用-verilog_HDL-four lookahead adder, learning materials, you can easily use
Platform: | Size: 24576 | Author: fantong | Hits:

[VHDL-FPGA-Verilog] adder

Description: 实验要求：（1）画出5位逐级进位和超前进位加法器的电路图，要求在图中表明输入、输出信号、中间信号等全部相关的信号，且信号命名应和图中的标注一一对应；（2）不能使用课本中的FOR循环语句，VHDL的赋值语句应和电路图一一对应；（3）VHDL代码和仿真波形要保存。（4）关于超前进位加法器，可以参照课本P160设计。（5）要求提交设计报告，按照深大实验报告的标准格式，同时需要代码，仿真结果和综合电路图。 -The experimental requirements: (1) to draw the 5 cascaded carry and circuit diagrams of carry look ahead adder, required to indicate signal input, output signal, the intermediate signal and all other related in the figure, and the signal should be named annotation and figure one one corresponding (2) can not be used textbooks in the FOR loop statement, the assignment statement of VHDL should be and the circuit in figure one one correspond (3) VHDL code and the simulation waveform to save. (4) on the carry lookahead adder, can reference books P160 design. (5) required to submit the design report, in accordance with the standard format deep experimental report, also need to code, the simulation results and the integrated circuit diagram.
Platform: | Size: 36864 | Author: Jin | Hits:

[Other] carry-look-ahead

Description: it's implementation for carry lookahead adder in vhdl
Platform: | Size: 552960 | Author: hosseinkhani | Hits:

[VHDL-FPGA-Verilog] 32-bit Carry lookahead adder

Description: 32-bit Carry lookahead adder generic verilog
Platform: | Size: 954 | Author: gsrwork2017@gmail.com | Hits:

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[WEB Code] ripple-lookahead-carryselect-adder

[Linux-Unix] cla_dc

[Linux-Unix] cla_src

[Documents] ripple-lookahead-carryselect-adder

[Linux-Unix] cla_dc

[Linux-Unix] cla_src

[Windows Develop] lookahead

[Other] adder

[Algorithm] CLAA_32_BITS

[VHDL-FPGA-Verilog] cla16

[VHDL-FPGA-Verilog] VHDL-ripple-lookahead-carryselect-adder

[VHDL-FPGA-Verilog] Lookahead-adder

[VHDL-FPGA-Verilog] carry-lookahead-adder

[VHDL-FPGA-Verilog] adder

[VHDL-FPGA-Verilog] lookahead-adder

[VHDL-FPGA-Verilog] ADDER

[Other] four-lookahead-adder

[VHDL-FPGA-Verilog] adder

[Other] carry-look-ahead

[VHDL-FPGA-Verilog] 32-bit Carry lookahead adder

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