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Description: mentor UART IP verilog源码 以通过验证.-mentor UART IP verilog source to the test.
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Size: 26110 |
Author: cray |
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Description: Mentor公司的ModelSim是业界最优秀的HDL语言仿真软件,它能提供友好的仿真环境,是业界唯一的单内核支持VHDL和Verilog混合仿真的仿真器。它采用直接优化的编译技术、Tcl/Tk技术、和单一内核仿真技术,编译仿真速度快,编译的代码与平台无关,便于保护IP核,个性化的图形界面和用户接口,为用户加快调错提供强有力的手段,是FPGA/ASIC设计的首选仿真软件。
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Size: 1009119 |
Author: t613@163.com |
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Description: mentor UART IP verilog源码 以通过验证.-mentor UART IP verilog source to the test.
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Size: 25600 |
Author: cray |
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Description: montor的system verilog培训教程-system verilog training material from mentor
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Size: 2855936 |
Author: huangluyang |
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Description: modelsim是Mentor graphics公司推出的HDL代码仿真工具,也是业界最流行的HDL仿真工具之一。支持图形界面操作和脚本操作。常见的图形界面操作相对直观,但是由于重复性操作几率高、处理效率低、工程的非保存性,对于大规模的代码仿真不推荐使用;脚本操作完全可以克服以上的缺点,把常见的命令,比如库文件和RTL加载、仿真、波形显示等命令编辑成.do脚本文件,只需要让Modelsim运行.do文件即可以完成仿真,智能化程度高。本文重点介绍Modelsim常见命令的使用,以及如何使用.do文件进行智能化的仿真。
参考文档:PKT.rar
-Modelsim is a very popular tool for simulating the verilog language and debugging. This paper focus to tell the basic script of modelsim and it can help to greatly improve our dugging efficency..
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Size: 374784 |
Author: liangyao |
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Description: Mentor公司的ModelSim是业界最优秀的HDL语言仿真软件,它能提供友好的仿真环境,是业界唯一的单内核支持VHDL和Verilog混合仿真的仿真器。-Mentor' s ModelSim is the industry' s best HDL language simulation software, it can provide a friendly simulation environment, the industry' s only single-kernel support for mixed VHDL and Verilog simulation of the simulator.
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Size: 388096 |
Author: 王阳 |
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Description: 非常好的Mentor catapult学习书, catabult 可用于高级综合,由c产生vhdl/verilog。 这本与systemC相关。-very nice book for catabult study
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Size: 37888 |
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Description: We present elliptic curve cryptography (ECC) coprocessor,
which is dual-field processor with projective
coordinator. We have implemented architecture for scalar
multiplication, which is key operation in elliptic curve
cryptography. Our coprocessor can be adapted both prime field
and binary field, also contains a control unit with 256 bit serial
and parallel operations , which provide integrated highthroughput
with low power consumptions. Our scalar multiplier
architecture operation is perform base on clock rate and produce
better performance in term of time and area compared to similar
works. We used Verilog for programming and synthesized using
Xilinx Vertex II Pro devices. Simulation was done with Modelsim
XE 6.1e, VLSI simulation software from Mentor Graphics
Corporation especially for Xilinx devices.
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Size: 116736 |
Author: 陳曉慧 |
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Description: verilog编写的关于使用MENTOR的MBISTArchitect进行momery的自测试代码,包含测试算法模型,SRAM,ROM模型-verilog prepared by the use of MBISTArchitect for momery MENTOR self-test code, including test algorithm model, SRAM, ROM model
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Size: 305152 |
Author: |
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Description: Mentor公司的ModelSim是业界最优秀的HDL语言仿真软件,它能提供友好的仿真环境,是业界唯一的单内核支持VHDL和Verilog混合仿真的仿真器。它采用直接优化的编译技术、Tcl/Tk技术、和单一内核仿真技术,编译仿真速度快,编译的代码与平台无关,便于保护IP核,个性化的图形界面和用户接口,为用户加快调错提供强有力的手段,是FPGA/ASIC设计的首选仿真软件。(Mentor's ModelSim, the industry's best HDL language simulation software, offers a friendly simulation environment and is the industry's only single-core simulator supporting VHDL and Verilog mixed simulations. It uses direct optimization of the compiler technology, Tcl / Tk technology, and a single kernel simulation technology, compile and emulate fast, compiled code has nothing to do with the platform, easy to protect IP core, personalized graphical interface and user interface to speed up the user to debug wrong Provide a powerful means of choice for FPGA / ASIC design simulation software.)
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Size: 523264 |
Author: 冰激凌很牛
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