Description: 一个用VerilogHDL语言编写的8X8的乘法器-a Verilog HDL language used in the preparation of the multiplier 8X8 Platform: |
Size: 17408 |
Author:胡东 |
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Description: verilog程序,实现两个16bit数乘法,采用booth算法,基于状态机实现,分层次为datapath和controller两个子模块,testBench测试通过-verilog procedures, two 16bit multiplication, the algorithm used booth. Based on the state machine achieved at different levels for datapath controller and two sub-modules, testBench the test Platform: |
Size: 2048 |
Author: |
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Description: 介绍了几种常用的乘法器的设计,carry_save_mult,ripple_carry_mult等,压缩包中包含结构流程图,用verilogHDL语言,采用modelsim仿真验证-This paper introduces some commonly used multiplier design, carry_save_mult, ripple_carry_mult such as, compressed package that contains the structure of flow chart, using verilogHDL language, using ModelSim simulation Platform: |
Size: 266240 |
Author:yaoyongshi |
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Description: 64位乘法器,超前进位的,大家看看,通过仿真的,verilog的-64-bit multiplier, bit-ahead, let us look at the adoption of simulation, verilog of Platform: |
Size: 37888 |
Author: |
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Description: 介绍了一种64位子字并行乘法器的设计。根据不同的操作模式可以完成普通模式操作即64bit*64bit乘法操作,又可完成子字并行操作模式,即4个16bit*16bit乘法操作。-Introduced a 64-seat word parallel multiplier design. Depending on the operating mode Normal mode operation can be done that 64bit* 64bit multiplication operations, but also to complete the sub-word parallel operation mode, that is, four 16bit* 16bit multiplication operation. Platform: |
Size: 99328 |
Author:余娅 |
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