Welcome！[Sign In] ！[Sign Up]！
Front-page it | Collect it | [中国-简体中文]
FAQ Fav
Location:
Search - PLL pdf

Search list

[Develop Tools] LC72131

Description: LC72131 PDF-Sanyo PLL chip LC72131 datasheet.
Platform: | Size: 343772 | Author: nana | Hits:

[Other resource] PLL

Description: 国外一篇很好的数字锁相环（PLL）设计文档（解压后PLL.pdf），不可不看呦！
Platform: | Size: 352799 | Author: li | Hits:

[ARM-PowerPC-ColdFire-MIPS] PLL_and_DLL（台湾版）.pdf

Description: 目前最简单易懂的PLL讲义（中文版）
Platform: | Size: 1754080 | Author: mvvk@sohu.com | Hits:

[Books] LC72131

Description: LC72131 PDF-Sanyo PLL chip LC72131 datasheet.
Platform: | Size: 343040 | Author: nana | Hits:

[Communication-Mobile] DDS+PLL

Description: 基于FPGA的新的DDS+PLL时钟发生器-FPGA-based new DDS PLL clock generator
Platform: | Size: 145408 | Author: 李敏 | Hits:

[assembly language] TEA5767inf

Description: SP3767hl源码，很详细的！！！！和tea5767相类似-SP3767hl source, very detailed! ! ! ! And similar TEA5767
Platform: | Size: 1897472 | Author: | Hits:

[Software Engineering] PLL

Description: 国外一篇很好的数字锁相环（PLL）设计文档（解压后PLL.pdf），不可不看呦！-Abroad, a good digital phase-locked loop (PLL) design documents (after extracting PLL.pdf), can not look at Yo!
Platform: | Size: 352256 | Author: | Hits:

[VHDL-FPGA-Verilog] pll

Description: 收集的数字锁相环设计相关文章多篇.主要采用VHDL语言进行设计.-Collection of digital phase-locked loop design articles related articles. Mainly VHDL design languages.
Platform: | Size: 10079232 | Author: gk | Hits:

[SCM] MAX7044

Description: MAX7044是基于晶振PLL 的VHF/UHF发射器芯片，在300 MHz～450 MHz频率范围内发射OOK/ASK数据，数据速率达到100 kbps，输出功率+13 dBm(50Ω负载)，电源电压+2.1～+3.6 V，电流消耗在2.7 V时仅7.7 mA。工作温度范围一40℃～＋125℃，采用3 mm×3 mm SOT23 - 8封装。 MAX7033是一个完全集成的低功耗CMOS超外差接收器芯片，接收频率范围在300 MHz～450 MHz的ASK信号。接收器射频输入信号范围从一114 dBm-0dBm。MAX7033芯片内部包含有LNA、差分镜像抑制混频器、PLL、VCO、10.7 MHz IF限幅放大器、AGC、RSSI、模拟基带数据信号恢复等电路。工作电压+3.3 V或+5.0V，250μs启动时间，低功耗模式电流消耗<3.5μA，工作温度-40℃～＋105℃，采用TSSOP-28和薄形QFN-EP* *-32封装。 MAXT044发射器芯片与接收器芯片MAX7033配套，适合汽车遥控、无键进入系统、安防系统、车库门控制、家庭自动化、无线传感器等应用。 -MAXT044发射器芯片与接收器芯片MAX7033配套，适合汽车遥控、无键进入系统、安防系统、车库门控制、家庭自动化、无线传感器等应用。
Platform: | Size: 173056 | Author: backoff | Hits:

[Communication-Mobile] Mod-Demod-FM

Description: it is and Modulator and Demolator on FM, it helps you to build it with a VCO and a PLL LM565
Platform: | Size: 81920 | Author: Hellemperor | Hits:

[Other] ChargePumpPLL

Description: An Analysis and Performance Evaluation of a Passive Filter Design Technique for Charge Pump PLL.pdf This paper investigates the design of passive loop filters for Frequency Synthesizers utilizing a Phase- Frequency Detector and a current switch charge pump.-An Analysis and Performance Evaluation of a Passive Filter Design Technique for Charge Pump PLL.pdf This paper investigates the design of passive loop filters for Frequency Synthesizers utilizing a Phase-Frequency Detector and a current switch charge pump.
Platform: | Size: 129024 | Author: 刘洋 | Hits:

[Other] PLL

Description: simulink 仿真锁相环的一个pdf-a pdf of pll using simulink
Platform: | Size: 4389888 | Author: Edison | Hits:

[Software Engineering] PLL(pdf)

Description: 锁相环的设计方法介绍（PLL），可作为设计的参考。-Design method for PLL (PLL), can be used as a reference design.
Platform: | Size: 73728 | Author: 李强 | Hits:

[VHDL-FPGA-Verilog] sdram

Description: 通过 UART 读写 SDRAM verilog 源代码 通过 UART 的接口发送命令来读写 SDRAM 命令格式如下： 00 02 0011 1111 2222 00： 写数据 02： 写个数 0011： 写地址 1111 2222： 写数据， 是 16 bit， 每写完一个数据，向串口发送 FF 回应； 输出： FF FF 01 03 0044 01: 读sdram 03： 读的个数 0044: 读的地址 输出： xxxx xxxx xxxx sdram 在 0044 0045 0046 处的数据； sdram 使用的是 K4S161622D.pdf 系统时钟 25m， 通过 PLL 得到 SDRAM clk 100m sdram controller clk 100m， 前者相对后者2ns 相移 -Read and write through the UART SDRAM verilog source code through the UART interface to send commands to SDRAM read and write command format is as follows: 0,002,001,111,112,222 00: Write Data 02: Write the number of 0011: write address 11112222: write data, is 16 bit, each completed a data, respond to the serial port FF output: FF FF 01 03 0044 01: Reading sdram 03: 0044 the number of read: Read the address output: xxxx xxxx xxxx sdram at 004,400,450,046 at the data sdram use system clock is K4S161622D.pdf 25m, obtained by PLL SDRAM clk 100m sdram controller clk 100m, the former phase shift relative to the latter 2ns
Platform: | Size: 14336 | Author: 周西东 | Hits:

[matlab] PLL-and-FLL-in-digital-costas-loop

Description: 锁相环和锁频环在数字costas环中的应用.pdf 一篇关于costa环路的新颖设计方案，包含大量的仿真图和性能分析，对学习锁相环有很大帮助-And frequency-locked loop PLL digital costas loop in the application. Pdf a novel about the costa loop design, contains a large number of simulation map and performance analysis are very helpful for learning PLL
Platform: | Size: 781312 | Author: sunnysnowhi | Hits:

[Linux-Unix] imx6q-cpufreq

Description: The setpoints are selected per PLL PDF frequencies, so we need to reprogram PLL for frequency scaling.
Platform: | Size: 2048 | Author: poucengcer | Hits:

[Other] TB31206

Description: 东芝公司开发的一款锁相环PLL芯片，可以用于频率综合使用。(Toshiba Co developed a PLL PLL chip, can be used for frequency integrated use)
Platform: | Size: 435200 | Author: zhangdbl | Hits:

[SCM] ADF4351-精简(点频)-资料包+PDF

Description: 锁相环模块的相关驱动级一个实际应用的例子和相关的文档(The related driver level of the PLL module, an example of practical application and related documents)
Platform: | Size: 17826816 | Author: 安珍妮 | Hits:

[Other] Lab2_M9_PLL_application.pdf

Description: Phase Locked Loop Lab Experiment
Platform: | Size: 138240 | Author: eng_abdallah | Hits:

[Other] ADF4350.pdf

Description: The ADF4350 allows implementation of fractional-N or integer-N phase-locked loop (PLL) frequency synthesizers if used with an external loop filter and external reference frequency.
Platform: | Size: 801792 | Author: kadomcevvn86 | Hits:
« 12 »

CodeBus www.codebus.net