sdram Read and write through the UART SDRAM verilo

Title: sdram

Category:
VHDL-FPGA-Verilog
Tags:
[VHDL] [源码]
File Size:
14kb
Update:
2012-11-26
Downloads:
0 Times
Uploaded by:
ucs.xidong

Description: Read and write through the UART SDRAM verilog source code through the UART interface to send commands to SDRAM read and write command format is as follows: 0,002,001,111,112,222 00: Write Data 02: Write the number of 0011: write address 11112222: write data, is 16 bit, each completed a data, respond to the serial port FF output: FF FF 01 03 0044 01: Reading sdram 03: 0044 the number of read: Read the address output: xxxx xxxx xxxx sdram at 004,400,450,046 at the data sdram use system clock is K4S161622D.pdf 25m, obtained by PLL SDRAM clk 100m sdram controller clk 100m, the former phase shift relative to the latter 2ns

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File list (Check if you may need any files):

pll_ctrl.v
pll_ctrl_bb.v
pll_ctrl_syn.v
sdr_ctrl.v
sdr_param.v
sdr_test_top.sdc
sdr_test_top.v
sys_ctrl.v
uart_clk.v
uart_recv.v
uart_send.v
uio_ctrl.v

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