Description: Procedure Note: In this experiment, control development board to complete the above SDRAM read and write capabilities. SDRAM write data inside first and then read out the data to compare, if you do not match on the adoption of LED variable light display, if agreed, LED does not light. part1 is to use Modelsim simulation project part2 the top spot verification in the development of the project directory Description: part1: part1_32 is 4m32SDRAM simulation project part1_16 is 4m16SDRAM simulation works \ model folder, which is a simulation model \ rtl folder, which is the source file \ sim is a simulation project inside the folder \ test_bench folder which is a test file \ wave inside the folder is a simulation waveform
File list (Check if you may need any files):
s16_sdram\introduce.txt
.........\part1\part1_32\model\mt48lc2m32b2.v
.........\.....\........\rtl\Command.v
.........\.....\........\...\control_interface.v
.........\.....\........\...\Params.v
.........\.....\........\...\sdr_data_path.v
.........\.....\........\...\sdr_sdram.v
.........\.....\........\sim\Command.v
.........\.....\........\...\control_interface.v
.........\.....\........\...\mt48lc2m32b2.v
.........\.....\........\...\Params.v
.........\.....\........\...\sd32try.cr.mti
.........\.....\........\...\sd32try.mpf
.........\.....\........\...\sdram_test_tb.v
.........\.....\........\...\sdr_data_path.v
.........\.....\........\...\sdr_sdram.v
.........\.....\........\...\sdtry.cr.mti
.........\.....\........\...\vsim.wlf
.........\.....\........\...\wave.do
.........\.....\........\...\.ork\command\verilog.asm
.........\.....\........\...\....\.......\_primary.dat
.........\.....\........\...\....\.......\_primary.vhd
.........\.....\........\...\....\..ntrol_interface\verilog.asm
.........\.....\........\...\....\.................\_primary.dat
.........\.....\........\...\....\.................\_primary.vhd
.........\.....\........\...\....\mt48lc2m32b2\verilog.asm
.........\.....\........\...\....\............\_primary.dat
.........\.....\........\...\....\............\_primary.vhd
.........\.....\........\...\....\sdram_test_tb\verilog.asm
.........\.....\........\...\....\.............\_primary.dat
.........\.....\........\...\....\.............\_primary.vhd
.........\.....\........\...\....\..._data_path\verilog.asm
.........\.....\........\...\....\.............\_primary.dat
.........\.....\........\...\....\.............\_primary.vhd
.........\.....\........\...\....\....sdram\verilog.asm
.........\.....\........\...\....\.........\_primary.dat
.........\.....\........\...\....\.........\_primary.vhd
.........\.....\........\...\....\_info
.........\.....\........\test_bench\sdram_test_tb.v
.........\.....\........\wave\32wave.bmp
.........\.....\....2_16\model\mt48lc8m16a2.v
.........\.....\........\rtl\Command.v
.........\.....\........\...\control_interface.v
.........\.....\........\...\Params.v
.........\.....\........\...\sdr_data_path.v
.........\.....\........\...\sdr_sdram.v
.........\.....\........\sim\Command.v
.........\.....\........\...\control_interface.v
.........\.....\........\...\mt48lc8m16a2.v
.........\.....\........\...\Params.v
.........\.....\........\...\sdram_test_tb.v
.........\.....\........\...\sdr_data_path.v
.........\.....\........\...\sdr_sdram.v
.........\.....\........\...\sdtest.cr.mti
.........\.....\........\...\sdtest.mpf
.........\.....\........\...\vish_stacktrace.vstf
.........\.....\........\...\vsim.wlf
.........\.....\........\...\work\command\verilog.asm
.........\.....\........\...\....\.......\_primary.dat
.........\.....\........\...\....\.......\_primary.vhd
.........\.....\........\...\....\..ntrol_interface\verilog.asm
.........\.....\........\...\....\.................\_primary.dat
.........\.....\........\...\....\.................\_primary.vhd
.........\.....\........\...\....\mt48lc8m16a2\verilog.asm
.........\.....\........\...\....\............\_primary.dat
.........\.....\........\...\....\............\_primary.vhd
.........\.....\........\...\....\sdram_test\verilog.asm
.........\.....\........\...\....\..........\_primary.dat
.........\.....\........\...\....\..........\_primary.vhd
.........\.....\........\...\....\.........._tb\verilog.asm
.........\.....\........\...\....\.............\_primary.dat
.........\.....\........\...\....\.............\_primary.vhd
.........\.....\........\...\....\..._data_path\verilog.asm
.........\.....\........\...\....\.............\_primary.dat
.........\.....\........\...\....\.............\_primary.vhd
.........\.....\........\...\....\....sdram\verilog.asm
.........\.....\........\...\....\.........\_primary.dat
.........\.....\........\...\....\.........\_primary.vhd
.........\.....\........\...\....\test\verilog.asm
.........\.....\........\...\....\....\_primary.dat
.........\.....\........\...\.
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