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[Other resource] SRAM@DMA实验

Description: ALTERA NIOS处理器实验，QUARTUS下用VHDL编译成处理器，然后NIOS　SHELL下C 语言运行。实验SRAM和DMA调度-Altera NIOS processor experiments QUARTUS using VHDL compiler into processor, then NIOS SHELL C language runtime. Experimental SRAM and DMA Scheduling
Platform: | Size: 34569 | Author: xf | Hits:

[Other resource] SPI接口音频Codec实验

Description: ALTERA NIOS处理器，VHDL语言在QUARTUS编译通过，然后有C语言在NIOS SHELL下驱动，实验音频解码-Altera NIOS processor, the QUARTUS VHDL compiler, then the C language under NIOS SHELL-driven, experimental audio decoder
Platform: | Size: 34889 | Author: xf | Hits:

[ELanguage] lc2

Description: this a pack include source code for quartus 2. It is an implementation of the LC2. The LC-2 computer is described in Introduction to Computing Systems from Bits & Gates to C & Beyond by Yale Patt and Sanjay Patel, McGraw Hill, 2001. The LC2 model can be run as a simulation or downloaded to the UP3 in a larger model, TOP_LC2 that adds video output. Push buttons reset and single step the processor and a video output display of registers is generated. This state machine VHDL-based model of the LC-2 includes all source files. Currently compiled for a Cyclone EP1C6Q240 FPGA.
Platform: | Size: 43004 | Author: ngzhongsyen | Hits:

[GDI-Bitmap] picturebrowser

Description: README for Picturebrowser ========================= The modified files are included as listed in the final report: -alt_ypes.h : header file for io.h -nxview.c: modified this existing, to time the running time of the display -picturebrowser.c: file which handles the logic of buttoons and the driver (button) -hardware (folder): find the project inside and install on the board -jddctmgr.c : modified manager -jdidcint.c: hardware assisted idct transform -Makefile: to compile picturebrowser (you will have to include in romfs to run our project) -io.h -zImage Running our picture viewer: -------------------------- open the project (in hardware folder) with quartus and in programmer install on the board. In the terminal: $ nio2-download -g zImage and the start nios2-terminal $ nios2-terminal at Boot, it detects the USB and run ./pictureviewer Navigate through buttons...enjoy it with moderation:)
Platform: | Size: 2482 | Author: slmsw | Hits:

[VHDL-FPGA-Verilog] SRAM@DMA实验

Description: ALTERA NIOS处理器实验，QUARTUS下用VHDL编译成处理器，然后NIOS　SHELL下C 语言运行。实验SRAM和DMA调度-Altera NIOS processor experiments QUARTUS using VHDL compiler into processor, then NIOS SHELL C language runtime. Experimental SRAM and DMA Scheduling
Platform: | Size: 33792 | Author: xf | Hits:

[VHDL-FPGA-Verilog] qqq

Description: 数字滤波器的vhdl源代码.在quartus上运行过,里面还有matlab的仿真文件.-Digital filter of the VHDL source code. In Quartus run-off, along with the simulation matlab file.
Platform: | Size: 26624 | Author: 萧勇 | Hits:

[VHDL-FPGA-Verilog] vhdl_crc

Description: 在quartus中用VHDL语言开发的crc校验-Quartus VHDL language used in the development of CRC Checksum
Platform: | Size: 163840 | Author: 夏杰 | Hits:

[Software Engineering] mycpu

Description: Quartus II 5.0下写的一个单总线架构的CPU设计，包括控制器、运算器、译码电路等。模拟的时钟脉冲也给出。已经通过Quartus II 5.0运行。可以给需要设计总线架构CPU的同学一点参考。-Quartus II 5.0 written under a single bus architecture of the CPU design, including controllers, computing devices, such as decoding circuitry. Simulated clock pulse is also given. Has been run through the Quartus II 5.0. Can be addressed to the need to design bus architecture students CPU reference point.
Platform: | Size: 800768 | Author: 陈佳 | Hits:

[VHDL-FPGA-Verilog] pwm-c

Description: 用VHDL编写的PWM控制程序，通过寄存器控制20余路PWM输出；qar是quartus的压缩包格式-VHDL prepared using PWM control procedures, through the registers to control more than 20 road PWM output qar is Quartus compressed packet format
Platform: | Size: 119808 | Author: mu | Hits:

[Embeded-SCM Develop] NIOS_LED

Description: 完整的Nios 2 演示工程，包括Quartus II 工程和NIOS IDE下的c代码。采用NIOS 2处理器控制LED。已通过实验测试。-Complete Nios 2 demonstration projects, including the Quartus II and NIOS IDE works under the c code. NIOS 2 processor to control the use of LED. Experimental tests have passed.
Platform: | Size: 763904 | Author: M | Hits:

[VHDL-FPGA-Verilog] FSKmodulationanddemodulation

Description: FSK调制与解调，整个设计基于ALTERA公司的QuartusⅡ开发平台，并用Cyclone系列FPGA实现。所设计的调制解调器具有体积小、功耗低、集成度高、软件可移植性强、扰干扰能力强的特点,符合未来通信技术设计的方向。-FSK modulation and demodulation, the entire design is based on ALTERA' s development platform Quartus Ⅱ, and Cyclone series FPGA implementation. Designed by the modem with a small size, low power consumption, high integration, software portability, and strong interference immunity characteristics consistent with the design of future communication technology direction.
Platform: | Size: 575488 | Author: 张继峰 | Hits:

[VHDL-FPGA-Verilog] fifo_Cprogram

Description: 应用于nios中的FIFO程序及连接图，开发环境为quartus-c program fifo in nios
Platform: | Size: 5120 | Author: planet1997 | Hits:

[VHDL-FPGA-Verilog] DE2_NET

Description: 用DE2开发板实现的网络控制器。硬件用Verilog语言编写，在Quartus上编译；软件用C语言编写，在Nios2上编译运行。程序已经过测试，功能完好。-DE2 development board with the realization of the network controller. Hardware using Verilog language, compiled in the Quartus software with C language, compiled to run in Nios2. Procedure has been tested, function well.
Platform: | Size: 1601536 | Author: 符玉襄 | Hits:

[ARM-PowerPC-ColdFire-MIPS] LED

Description: 在ALTERA的DE 2 开发板上做的一个类似闪烁的彩灯，用了16个LEDR，可以直接下载到板子上运行，基于经典的开发平台Quartus II+SOPC Builder+Nios II IDE 做的，只要看了以后，你就会自己设计各种花样的彩灯闪烁的样子了.所用语言有多种，VHDL,C/C++等-DE 2 in the development of the ALTERA board to do a similar flickering lantern, with a 16 LEDR, can be directly downloaded to the board on the operation of the development platform based on the classic Quartus II+ SOPC Builder+ Nios II IDE to do, just have to look at After, you will design their own patterns of lanterns flicker the same again. There are a variety of language, VHDL, C/C++, etc.
Platform: | Size: 4208640 | Author: liguoyin | Hits:

[VHDL-FPGA-Verilog] sopcIIC

Description: 该例子是基于sopc的IIC总线设计完整设计，分为硬件和软件部分，软件部分是用c语言编写的。该项目是个以完成的项目，据有较高的参考和经济价值。该例子是原来做过的项目。 整个项目是在Quartus II 7.0和nios IDE环境下开发。-This example is based on the IIC bus design sopc complete design, divided into hardware and software, the software part is written in c language. The project is to complete the project, according to the reference and a higher economic value. The example is a project originally done. The whole project is in the Quartus II 7.0 and the nios IDE development environment.
Platform: | Size: 13532160 | Author: bobo | Hits:

[VHDL-FPGA-Verilog] mips

Description: MIPs CPU，VERILOG代码，经过QUARTUS综合，时序分析，验证无误。-MIPS CPU
Platform: | Size: 5120 | Author: 王龙 | Hits:

[VHDL-FPGA-Verilog] CPU

Description: 一个多周期CPU的完整设计，quartus平台，Verilog实现，内含实验报告，和详细的各模块功能表-Complete a multi-cycle CPU design, quartus platform, Verilog implementation, includes lab reports, and a detailed menu of each module
Platform: | Size: 6606848 | Author: 涯 | Hits:

[VHDL-FPGA-Verilog] Sn_Quartus

Description: Synthesizerr frequency VHDL Quartus 90.
Platform: | Size: 122880 | Author: Booda | Hits:

[matlab] matlab与Quartus II接口

Description: matlab与Quartus II接口 Copyright (c) 2009, Sreeram Mohan All rights reserved. Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met
Platform: | Size: 5108 | Author: slaceware@sina.com | Hits:

[Console] ceilf

Description: Ceif test C for windows and Quartus C
Platform: | Size: 113664 | Author: guerrilla | Hits:
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