Search - Quartus I2C

[Embeded-SCM Develop] sd_audio_aic23

Description: SD卡和AIC23数字音频输出实验, FreeDev Audio Dsp Board采用了TI公司的TVL320AIC23 1、控制接口使用I2C，Quartus中将CS置低（器件地址0011010）。 2、数字音频接口使用了组件FreeDev_aic23,有三种测试和应用模式，中断结合DMA方式能在NIOS II中采集和发送数据。中断信号产生于模块中FIFO缓冲区的半满信号，读取数据端口自动清除中断请求信号。 3、I2C IP 和FreeDev_aic23 IP分别在Quartus 工程目录中 4、SD卡读写通过SD_DAT0、SD_CLK、SD_CMD三个PIO信号线用软件控制时序。 5、该范例读SD卡数据，通过DMA将Buffer数据送到FreeDev_aic23的 FIFO中实现数据播放。 6、SD卡中的数据必须是以48K*16bit保存的采样数据。数据可以通过SD读卡器写入。
Platform: | Size: 13312 | Author: HuFengzhang | Hits:

[Embeded-SCM Develop] i2c_IP

Description: altera 的i2c ip核，可直接调用在quartus中把库指向文件位置就可-altera the i2c ip nuclear, can be directly called in the Quartus point in the database file location can be
Platform: | Size: 7168 | Author: 李涛 | Hits:

[Embeded-SCM Develop] an494_design_example

Description: I2C to GPIO Port expander的Verilog HDL 程序原码，直接可在Quartus环境下运行。-I2C to GPIO Port expander procedures of the Verilog HDL source code directly in the Quartus environment.
Platform: | Size: 279552 | Author: wangyunshann | Hits:

[VHDL-FPGA-Verilog] i2c_slv_ctrl

Description: I2c总线 verilog实现，可用于quartus设计-Verilog bus I2c realized, can be used to design quartus
Platform: | Size: 1024 | Author: cloudy | Hits:

[VHDL-FPGA-Verilog] altera_avalon_i2c_V90

Description: I2C IP for Quartus V9.0, can used in SOPC builder.
Platform: | Size: 12288 | Author: homeuser | Hits:

[VHDL-FPGA-Verilog] altera_avalon_i2c_V91

Description: I2C IP for Quartus V9.0 sp1, can used in SOPC builder.-I2C IP for Quartus V9.0, can used in SOPC builder.
Platform: | Size: 12288 | Author: homeuser | Hits:

[VHDL-FPGA-Verilog] oc_i2c_master_top_v92

Description: I2C IP for Quartus V9.0 sp2, can used in SOPC builder.
Platform: | Size: 3072 | Author: homeuser | Hits:

[VHDL-FPGA-Verilog] oc_i2c_master_byte_ctrl_v92

Description: I2C IP for Quartus V9.0 sp2, can used in SOPC builder.
Platform: | Size: 3072 | Author: homeuser | Hits:

[VHDL-FPGA-Verilog] components

Description: quartus的几个IP核（PWM,RAM,I2C）-quartus several IP core (PWM, RAM, I2C)
Platform: | Size: 226304 | Author: 宋瑞 | Hits:

[VHDL-FPGA-Verilog] i2c_bus

Description: i2c总线控制器的verilog的实现，编译环境quartus-i2c bus controller verilog implementation, build environment quartusII
Platform: | Size: 496640 | Author: 杜征宇 | Hits:

[Communication] ch17_I2C

Description: I2C总线协议，可以在quartus上仿真综合，通用性比较好-I2C bus protocol, the simulation can be integrated in quartus, better versatility
Platform: | Size: 421888 | Author: tanglei | Hits:

[VHDL-FPGA-Verilog] mcu-fpga

Description: 目录 FPGA & MCU 开发板介绍实验1 QuartusII 软件应用实验2 Keil C51 应用实验3 字符型LCD YM1602 的应用实验4 带字库的中文LCD YM12864 的应用实验5 时钟芯片DS1302 的应用实验6 I2C 总线器件AT24C64 的应用实验7 数字温度传感器的应用实验8 行列式键盘实验9 硬件电子琴的设计实验10 AD 与DA 的使用实验11 简易DDS 信号源设计实验12 用模拟示波器显示多路波形实验13 Quartus Ⅱ 内嵌逻辑分析仪SignalTap Ⅱ的使用附录1 FPGA 驱动程序下载线安装步骤附录2 YM12864 指令表附录3 开发板原理图-Catalog FPGA & MCU Development Board introduced the software application test experiment 1 QuartusII 2 Keil C51 character LCD YM1602 Application Experiment 3 Experiment 4, the application of the Chinese character LCD YM12864 with the application of experimental application of 5 DS1302 clock chip experiment 6 I2C bus devices AT24C64 the Application of experimental application of digital temperature sensor 7 Experiment 8 Experiment 9 determinant hardware keyboard keyboard design experiments 10 AD and the DA' s 11 easy to use experimental design experiments DDS signal source 12 with the analog oscilloscope waveform display multiple experiments embedded logic analyzer 13 Quartus Ⅱ the use of instruments SignalTap Ⅱ Appendix 1 FPGA download cable driver installation steps in Appendix 2 YM12864 instruction sheet Appendix 3 development board schematics
Platform: | Size: 1640448 | Author: lyy | Hits:

[VHDL-FPGA-Verilog] Verilog-IIC

Description: VerilogHDL语言编写的IIC 读写试验程序, 在Quartus II 8.1下面调试通过 -IIC VerilogHDL languages to read and write test procedures, the Quartus II 8.1 debugging through the following
Platform: | Size: 473088 | Author: Joseph | Hits:

[VHDL-FPGA-Verilog] I2C

Description: 语言：verilog 功能：用Verilog HDL编写的I2C主机串行通信的程序。两条总线线路：一条串行数据线 SDA，一条串行时钟线 SCL；串行的 8 位双向数据传输位速率在标准模式下可达 100kbit/s，快速模式下可达 400kbit/s ，高速模式下可达 3.4Mbit/s；在数据传输过程中，当时钟线为高电平时，数据线必须保持稳定。如果时钟线为高电平时数据线电平发生变化，会被认为是控制信号。仿真工具：modelsim 综合工具：quartus -Language: verilog Function: I2C written in Verilog HDL with the host serial communication program. Two bus lines: a serial data line SDA, a serial clock line SCL 8-bit bi-directional serial data transmission bit rate in the standard mode of up to 100kbit/s, fast mode, up to 400kbit/s, high-speed mode of up to 3.4Mbit/s in the data transmission process, when the clock line is high, the data line must remain stable. If the clock line is high level when the data line changes will be considered is the control signal. Simulation tools: modelsim synthesis tool: quartus II
Platform: | Size: 8192 | Author: huangjiaju | Hits:

Category

Source Code

Web/Internet

Develop Tools

Document

Other

Search in results

OS

Platform

Language

File Type

Search list

[Embeded-SCM Develop] sd_audio_aic23

[Embeded-SCM Develop] i2c_IP

[Embeded-SCM Develop] an494_design_example

[VHDL-FPGA-Verilog] i2c_slv_ctrl

[VHDL-FPGA-Verilog] altera_avalon_i2c_V90

[VHDL-FPGA-Verilog] altera_avalon_i2c_V91

[VHDL-FPGA-Verilog] oc_i2c_master_top_v92

[VHDL-FPGA-Verilog] oc_i2c_master_byte_ctrl_v92

[VHDL-FPGA-Verilog] components

[VHDL-FPGA-Verilog] i2c_bus

[Communication] ch17_I2C

[VHDL-FPGA-Verilog] mcu-fpga

[VHDL-FPGA-Verilog] Verilog-IIC

[VHDL-FPGA-Verilog] I2C

[VHDL-FPGA-Verilog] i2c

[VHDL-FPGA-Verilog] I2C

[VHDL-FPGA-Verilog] i2c_ctrl

[VHDL-FPGA-Verilog] i2c

[VHDL-FPGA-Verilog] I2C

[VHDL-FPGA-Verilog] i2c

CodeBus www.codebus.net