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[Software Engineering] mycpu

Description: Quartus II 5.0下写的一个单总线架构的CPU设计，包括控制器、运算器、译码电路等。模拟的时钟脉冲也给出。已经通过Quartus II 5.0运行。可以给需要设计总线架构CPU的同学一点参考。
Platform: | Size: 800692 | Author: 陈佳 | Hits:

[Software Engineering] mycpu

Description: Quartus II 5.0下写的一个单总线架构的CPU设计，包括控制器、运算器、译码电路等。模拟的时钟脉冲也给出。已经通过Quartus II 5.0运行。可以给需要设计总线架构CPU的同学一点参考。-Quartus II 5.0 written under a single bus architecture of the CPU design, including controllers, computing devices, such as decoding circuitry. Simulated clock pulse is also given. Has been run through the Quartus II 5.0. Can be addressed to the need to design bus architecture students CPU reference point.
Platform: | Size: 800768 | Author: 陈佳 | Hits:

[Other] risc

Description: 基于quartus II软件 用verilog 语言描述的精简指令CPU-quartus II verilog
Platform: | Size: 1259520 | Author: xu | Hits:

[ARM-PowerPC-ColdFire-MIPS] pipeline

Description: 用Quartus II 设计的3级流水CPU，指令采用二次重叠执行方式-Quartus II design with three-stage pipeline CPU, instruction execution overlaps with the second time
Platform: | Size: 3028992 | Author: kevin | Hits:

[Other] PipelineCPU

Description: Quartus II 7.2环境中，采用硬件描述语言VHDL独立完成了基于MIPS指令集的32位RISC处理器的逻辑设计-quartusII mips pipeline 32bit cpu design
Platform: | Size: 847872 | Author: znl | Hits:

[VHDL-FPGA-Verilog] danzhouqiCPU

Description: VHDL单周期CPU设计,基于Quartus II 开发平台-VHDL single-cycle CPU design, Quartus II development platform based on
Platform: | Size: 1587200 | Author: 逆天之刃 | Hits:

[VHDL-FPGA-Verilog] parallel-output-controller-(POC)

Description: 并行输出控制器，实现CPU与打印机之间的通信，程序基于VHDL语言，内附完整实验报告与仿真图像-The purpose of this project is to design and simulate a parallel output controller (POC)which acts an interface between system bus and printer. The Altera’s Quartus II EDA tool is recommended and provided for simulation.
Platform: | Size: 74752 | Author: 陈鹏 | Hits:

[VHDL-FPGA-Verilog] cpu

Description: 一个简单的CPU设计，支持add，sub，mvi，mv四条指令，用Verilog语言编写，在Quratus II上编译通过，仿真正确。-A simple CPU design, support add, sub, mvi, mv four instructions, with the Verilog language, compiled by the Quratus II, the simulation is correct.
Platform: | Size: 931840 | Author: 姜涛 | Hits:

[VHDL-FPGA-Verilog] CPU

Description: 这是用Quartus II 6.0做的CPU实验，是计算机组成原理专题实验。-This is done using Quartus II 6.0 CPU experiment, experimental feature is the computer organization.
Platform: | Size: 309248 | Author: wangbluer | Hits:

[VHDL-FPGA-Verilog] CPU8085

Description: Intel 8085 CPU in Quartus II. Compiles saved in Quartus restore database xxx.qar
Platform: | Size: 236544 | Author: Christoffer | Hits:

[VHDL-FPGA-Verilog] 7.5.0

Description: 利用汇编语言，QUARTUS ii软件编写的模拟CPU工作原理的一个程序。主要功能有寄存器，存储器，总线的工作方式的模拟-The use of assembly language, QUARTUS ii software development, simulation of a CPU works program. Main function registers, memory, bus simulation work
Platform: | Size: 156672 | Author: 王大力 | Hits:

[VHDL-FPGA-Verilog] Nios

Description: 利用Quartus II实现基于Nios的CPU软核设计实现。包括基本原理和实现代码。-Make use of Quartus II realization to design a realization according to the Nios CPU soft pit.Include basic principle and carry out a code.
Platform: | Size: 465920 | Author: mr.liu | Hits:

[VHDL-FPGA-Verilog] led2

Description: nios ii 流水灯源程序，采用quartus ii 11.0,nios ii 11.0,qsys构建CPU，由本人亲自编写，并下载至电路板验证流水灯成功-nios ii water lights, quartus ii 11.0 nios ii 11.0 qsys build the CPU, I personally prepared and downloaded to the board verification of light water
Platform: | Size: 8006656 | Author: 王超 | Hits:

[Other Embeded program] MyC2Board_RS232_Test

Description: 这是一个Altera FPGA NIOS II RS232通讯程序。 在Quartus II工程中，用Qsys建立了一个NIOS II为核心的CPU系统，并挂接了一个RS232接口。 在software目录下，有三个工程，一个是用C++类包装的RS232类的Eclipse工程，一个是不用C++类包装的Eclipse工程，还有一个是用VC++2008编写的RS232测试工程。 VC++2008编写的工程运行在PC机上，与FPGA中的NIOS II通讯。 这个实验的主要目的是编写一个通用RS232类，这个类即可以用于NIOS II，又可以用于PC机，是一个可重用的RS232类；我们用这个类开发了不少以PC为控制平台，FPGA为硬件控制器的测试系统。 -This is an Altera FPGA NIOS II RS232 communication project. In the Quartus II project, there is a NIOS II CPU with RS232. In the Software directory, there are 3 projects. First one is an Eclipse Project with C++ RS232 Class. Second one is an Eclipse Project with C RS232.h. Other one is a VC++2008 Project with C++ RS232 Class. The purpose of this project is to write a RS232 Class use on any system needed RS232 communication. The RS232 Class not only use on NIOS II, but also use on PC. We used this RS232 Class on many Test Systems with PC and FPGA
Platform: | Size: 13864960 | Author: li hui xian | Hits:

[VHDL-FPGA-Verilog] duozhouqiCPU

Description: VHDL 多周期CPU设计。基于Quartus II平台-VHDL design of multi-cycle CPU. Quartus II-based platforms
Platform: | Size: 23856128 | Author: 逆天之刃 | Hits:

[VHDL-FPGA-Verilog] liushuixianCPU

Description: VHDL 流水线CPU的设计，基于Quartus II平台-VHDL design of pipelined CPU based on Quartus II platform
Platform: | Size: 2652160 | Author: 逆天之刃 | Hits:

[VHDL-FPGA-Verilog] cpu

Description: 8位实验CPU设计利用设计好的指令系统，编写汇编代码，以便测试所有设计的指令及指令涉及的相关功能。设计好测试用的汇编代码后，然后利用Quartus II软件附带的DebugController,编写汇编编译规则。接着，利用DebugController软件把汇编编译之后的二进制代码置入到所采用的存储器中，并对设计好的8位CPU进行测试。-Eight experiments designed CPU design using the instruction set, write assembly code in order to test all commands and instructions that involve the design of related functions. Design a good test of the assembly code, and then use the Quartus II software supplied DebugController, writing assembler rules. Next, the assembly DebugController software binary code compiled into the memory used, and the 8-bit CPU designed for testing.
Platform: | Size: 3375104 | Author: Bingo | Hits:

[VHDL-FPGA-Verilog] CPU

Description: 运用vhdl硬件描述语言在quartus II开发环境下独立设计与实现了基于精简指令集的五级流水线CPU的设计与实现。该流水CPU包括：取指模块，译码模块，执行模块，访存模块，写回模块，寄存器组模块，控制相关检测模块，Forwarding模块。该CPU在TEC-CA实验平台上运行，并且通过Debugcontroller软件进行单步调试，实验表明，该流水线CPU消除了控制相关、数据相关和结构相关。-Using vhdl hardware description language development environment under quartus II design and implementation of an independent design and implementation of a five-stage pipeline RISC-based CPU' s. The water CPU include: fetch module, decoding module, execution modules, memory access module, the write-back module, the register set of modules, control relevant to the detection module, Forwarding module. The CPU in the TEC-CA experimental platforms, and single-step debugging through Debugcontroller software, experiments show that the pipelined CPU eliminates the control-related, data-related and structurally related.
Platform: | Size: 822272 | Author: wang | Hits:

[ARM-PowerPC-ColdFire-MIPS] CPU

Description: 简单的CPU设计,使用VHDL 和 quartus ii 设计的cpu(a simply cpu design, vhdl quartus ii ,dsg gs h srh rsh rsh srjh srh)
Platform: | Size: 1488896 | Author: fgsdgsdg | Hits:

[SCM] cup实验指导书(1).docx

Description: cpu开发 单片机实现简单cpu的简单功能，使用quartus ii编程(cpu kaifa danpianji shixian jiandan cpu de jiandan gongneng shiyong quartus ii biancheng)
Platform: | Size: 61440 | Author: Hawi | Hits:

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