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Description: 直接频率合成,Quicklogic提供,部分源文件是Quicklogic 专用文件-direct frequency synthesis, pioneered provide some source document is dedicated ESP
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Size: 68450 |
Author: 陈旭 |
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Description: PCI总线仲裁参考设计,Quicklogic提供的verilog代码-PCI bus arbitration reference design, pioneered the Verilog code
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Size: 3480 |
Author: 陈旭 |
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Description: 这是quicklogic公司的直接频率合成(DDS)Verilog代码
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Size: 22732 |
Author: jinzhoulang |
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Description: 该文档是QUICKLOGIC的一篇关于用FPGA实现DDS的设计指导。
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Size: 46079 |
Author: cobain |
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Description: VHDL examples for counter design, use QuickLogic eclips
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Size: 1298336 |
Author: simingceng |
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Description: 直接频率合成,Quicklogic提供,部分源文件是Quicklogic 专用文件-direct frequency synthesis, pioneered provide some source document is dedicated ESP
Platform: |
Size: 68608 |
Author: 陈旭 |
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Description: PCI总线仲裁参考设计,Quicklogic提供的verilog代码-PCI bus arbitration reference design, pioneered the Verilog code
Platform: |
Size: 3072 |
Author: 陈旭 |
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Description: 这是quicklogic公司的直接频率合成(DDS)Verilog代码-QuickLogic Corporation This is a direct frequency synthesizer (DDS) Verilog code
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Size: 22528 |
Author: jinzhoulang |
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Description: 该文档是QUICKLOGIC的一篇关于用FPGA实现DDS的设计指导。-The document is an article on using the QuickLogic FPGA design guidance to achieve DDS.
Platform: |
Size: 46080 |
Author: cobain |
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Description: VHDL examples for counter design, use QuickLogic eclips
Platform: |
Size: 1298432 |
Author: simingceng |
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Description: Generic driver for QuickLogic devices. The only functions IRP_MJ_CREATE, IRP_MJ_CLEANUP and IRP_MJ_CLOSE are supported.
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Size: 2383872 |
Author: MasterOfOrion |
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