Welcome![Sign In][Sign Up]
Location:
Search - SCI VHDL

Search list

[Other resource2Dfft

Description: VHDL 关于2DFFT设计程序 u scinode1 ∼ scinode9.vhd: Every SCI node RTL vhdl code. The details can be seen in the following section. u 2dfft.vhd: The top module includes these scinodes and form a 3x3 SCI Torus network, and it support these sub-modules scinode1∼ scinode9 reset and clk and global_cnt signals to synchronous the sub-modules to simplify the overall design. u proj2.wfc: VSS simulation result that is the same as the ModelSim simulation result. u Pro2_2.wfc: VSS simulation result of another test pattern can’t cause overflow situation.-VHDL design procedures on 2DFFT u scinode1
Platform: | Size: 783292 | Author: 李成 | Hits:

[Other resourceSCI

Description: VHDL写的SCI接口。quartusII6.0的工程!
Platform: | Size: 195916 | Author: sunhao | Hits:

[VHDL-FPGA-Verilog2Dfft

Description: VHDL 关于2DFFT设计程序 u scinode1 ∼ scinode9.vhd: Every SCI node RTL vhdl code. The details can be seen in the following section. u 2dfft.vhd: The top module includes these scinodes and form a 3x3 SCI Torus network, and it support these sub-modules scinode1∼ scinode9 reset and clk and global_cnt signals to synchronous the sub-modules to simplify the overall design. u proj2.wfc: VSS simulation result that is the same as the ModelSim simulation result. u Pro2_2.wfc: VSS simulation result of another test pattern can’t cause overflow situation.-VHDL design procedures on 2DFFT u scinode1
Platform: | Size: 783360 | Author: 李成 | Hits:

[VHDL-FPGA-VerilogSCI

Description: VHDL写的SCI接口。quartusII6.0的工程!-SCI interface written in VHDL. quartusII6.0 works!
Platform: | Size: 195584 | Author: sunhao | Hits:

[VHDL-FPGA-VerilogVHDLbasicExampleDEVELOPEMENTsoursE

Description: 这里收录的是《VHDL基础及经典实例开发》一书中12个大型实例的源程序。为方便读者使用,介绍如下: Chapter3:schematic和vhdl文件夹,分别是数字钟设计的原理图文件和VHDL程序; Chapter4:multiplier文件夹,串并乘法器设计程序(提示:先编译程序包); Chapter5:sci文件夹,串行通信接口设计程序; Chapter6:watchdog文件夹,看门狗设计程序; Chapter7:taxi文件夹,出租车计价器设计程序; Chapter8:elevator文件夹,高层电梯控制器设计程序; Chapter9:cymometer1和cymometer2文件夹,前者是计数测频设计程序,后者是等精度测频设计程序; Chapter10:digital_lock文件夹,数字密码锁设计程序; Chapter11:I2C文件夹,I2C控制器设计程序; Chapter12:fifo文件夹,异步FIFO设计程序; Chapter13:dds文件夹,数字频率合成设计程序; Chapter14:vLA文件夹,虚拟逻辑分析仪设计程序。 -this book includes 12 detail examples of the source program
Platform: | Size: 139264 | Author: wuyu | Hits:

[VHDL-FPGA-Verilogsci

Description: VHDL编写的仿单片机串口通信程序,具有校验等功能-Written in VHDL simulation microcontroller serial communication program with checking functions
Platform: | Size: 110592 | Author: skysonya | Hits:

[VHDL-FPGA-Verilogsci_module

Description: verilog编写的串口模块,可以直接使用,已经成功用于产品上了。-UART by verilog.
Platform: | Size: 2048 | Author: 刘俊杰 | Hits:

[VHDL-FPGA-Veriloghsk4571_cuankou

Description: 串口通信SCI VHDL实现,在QUATTUS||9.0下编写,可在9.0及以上版本运行并下载,芯片为Altera的Cyclone3 EP3C8T1-Serial communication SCI VHDL realize, in QUATTUS | | 9.0 under preparation, can be run in the 9.0 and above versions and download, chips for Altera' s Cyclone3 EP3C8T144
Platform: | Size: 43008 | Author: hongsk | Hits:

CodeBus www.codebus.net