sci_module UART by verilog. - CodeBus

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VHDL-FPGA-Verilog

Title: sci_module

Category:
VHDL-FPGA-Verilog
Tags:
[VHDL] [源码]
File Size:
2kb
Update:
2012-11-26
Downloads:
0 Times
Uploaded by:
刘俊杰

Description: UART by verilog.

Downloaders recently: [More information of uploader 刘俊杰]

To Search: verilog sci_module verilog S SCI VHDL

[VerilogGrammarCheckmanual.Rar] - Verilog Grammar Check manual, it would b
[uart-verilog-vhdl] - with vhdl and verilog prepared by the se
[RS232uart(VHDL)] - Depth of 256-byte Serial RS232 procedure
[uart] - uart verilog
[uart_EP3C16_FIFO] - Programs for uart/RS232, it can receive
[decoder3_8] - Vhdl language to achieve through a simpl
[Rom_Control_FPGA] - Written in VHDL language using ROM contr
[jiafa] - for the newers to get familier with vhdl
[FPGA-CPLD] - FPGA-CPLD Development tutorial. Rar fpga

File list (Check if you may need any files):

send.v
rec.v

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