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Description: SDRAM控制器的VHDL实现,pdf格式,有需要多的,联系我-SDRAM controller VHDL, pdf format, it needs more, Contact
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Size: 125439 |
Author: 许春明 |
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Description: SDRAM控制器的VHDL实现,pdf格式,有需要多的,联系我-SDRAM controller VHDL, pdf format, it needs more, Contact
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Size: 124928 |
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Description: SDRAM控制器的设计与VHDL实现
是pdf格式的。在工程中实现过-SDRAM Controller Design with VHDL realize is pdf format. In the projects implemented
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Size: 138240 |
Author: hjx |
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Description: 动态随即存储器的时序和工作原理,剖析了其运行的状态机,对底层程序开发有帮助(例子是关于HY57V641620)-Then the dynamic memory timing and working principle, analyzes the state machine its running on the bottom of program development helpful (example is the HY57V641620)
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Size: 432128 |
Author: hlc |
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Description: cpld 控制 8-32M sdram 控制器 maxII epm570实现。
pdf 的说明文件-CPLD control 8-32M sdram controller maxII epm570 realize. pdf documentation
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Size: 192512 |
Author: 王可见 |
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Description: SATA NAS SOC,200MHz ARM926EJS核 SATA接口的NAS用处理器,集成USB2.0 HOST接口,Ethernet控制器,DDR SDRAM控制器,PCI HOST接口,可以扩展PCI外设。-SATA NAS SOC,NAS COntroller with 200MHz ARM926EJS core, intergated SATA controller,USB2.0 HOST controller,Ethernet MAC controller,DDR SDRAM controller,PCI HOST。
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Size: 974848 |
Author: gxliu |
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Description: 图像缓存是图像处理系统设计的重点和难点,包括SDRAM和FIFO的设计,本PDF是设计图像缓存设计的好资料-sdram and fifo design for real-time image processing system
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Size: 1146880 |
Author: 张荣奎 |
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Description: SDRAM的结构、时序与性能的关系.pdf
很难的的资料,值得一看。-SDRAM structure, timing and performance relationship. Pdf of the data difficult, worth a visit.
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Size: 545792 |
Author: 刘力军 |
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Description: 关于ddr sdram的一篇不错的文章,讲得挺详细的。-a good paper about ddr sdram,teaching you how to use ddr sdram.
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Size: 57344 |
Author: 张涛 |
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Description: DDR SDRAM设计及调试经验总结.pdf
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Size: 338944 |
Author: arens09 |
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Description: i2cinterface.v是我自己写的一段verilog代码,在接口为I2C接口的芯片设计中用到。送去流过片,仅作参考用。
debussy和modelsim协同仿真.txt 用于debussy和modelsim协同仿真时参考
RTL Coding and Optimization Guide for use with Design Compiler.pdf
数提讲座(1).wmv
数提讲座(2).wmv这两个视频和一篇文档对数字IC前端设计师的设计提高很有帮助,如果你觉得你到瓶颈状态了,想提高的话,强烈建议好好看看。
ADVANCED ASIC CHIP SYNTHESIS中文翻译资料.ppt这也是我极力推荐的,相信学习dc的人都知道原英文文档。这个ppt相当于翻译版,对dc和pt中文详细阐述。
基于DDR SDRAM控制时序分析的模型.pdf
全定制单元时序模型的建立.pdf 这两篇文档是用作建议时序模型的时候用作参考,是我花了小money买的哦。
数字IC设计全程实例.pdf 本文介绍了基于标准单元库的深亚微米数字集成电路的自动化设计流程。此流程从设计的系统行为级描述或RTL 级描述开始,依次通过系统行为级的功能验证,设计综合,综合后仿真,自动化布局布线,到最后的版图后仿真.
-i2cinterface.v a section of my own writing verilog code for the I2C interface in the interface used in chip design. Sent to flow through the film, only for reference.
debussy and modelsim co-simulation. txt for debussy and modelsim co-simulation reference
RTL Coding and Optimization Guide for use with Design Compiler.pdf
Mention the number of lectures (1). Wmv
Mention the number of lectures (2). Wmv the two videos, and the document is useful for the digital front-end IC designers to improve the design capability. if you think you go to bottleneck, and want to improve, then it is strongly recommended a good look.
ADVANCED ASIC CHIP SYNTHESIS Chinese translation of the information. Ppt that is what I strongly recommend, I believe that everyone learning dc knows its original English document. This ppt is equivalent to its translations.It elaborates the dc and pt in Chinese .
DDR SDRAM control the timing analysis based on the model. Pdf
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Size: 20989952 |
Author: 喻琪 |
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Description: SDRAM原理及时序分析,从网络上搜集,整理成PDF,对于嵌入式应用很有作用-SDRAM timing analysis principle, from the network to collect, organize into PDF, for the very role of embedded applications
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Size: 813056 |
Author: Clindax |
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Description: SDRAM-HY57V641620中文资料-SDRAM-HY57V641620
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Size: 432128 |
Author: paradise |
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Description: DDR SDRAM设计及调试经验总结.pdf-DDR SDRAM design and debug Experience. Pdf
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Size: 338944 |
Author: Mike |
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Description: DDR3 SDRAM datasheet please refer want to development DDR3 Controller
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Size: 1479680 |
Author: mil |
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Description: 通过 UART 读写 SDRAM verilog 源代码
通过 UART 的接口发送命令来读写 SDRAM
命令格式如下:
00 02 0011 1111 2222
00: 写数据
02: 写个数
0011: 写地址
1111 2222: 写数据, 是 16 bit, 每写完一个数据,向串口发送 FF 回应;
输出: FF FF
01 03 0044
01: 读sdram
03: 读的个数
0044: 读的地址
输出: xxxx xxxx xxxx
sdram 在 0044 0045 0046 处的数据;
sdram 使用的是 K4S161622D.pdf
系统时钟 25m, 通过 PLL 得到 SDRAM clk 100m
sdram controller clk 100m, 前者相对后者2ns 相移 -Read and write through the UART SDRAM verilog source code through the UART interface to send commands to SDRAM read and write command format is as follows: 0,002,001,111,112,222 00: Write Data 02: Write the number of 0011: write address 11112222: write data, is 16 bit, each completed a data, respond to the serial port FF output: FF FF 01 03 0044 01: Reading sdram 03: 0044 the number of read: Read the address output: xxxx xxxx xxxx sdram at 004,400,450,046 at the data sdram use system clock is K4S161622D.pdf 25m, obtained by PLL SDRAM clk 100m sdram controller clk 100m, the former phase shift relative to the latter 2ns
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Size: 14336 |
Author: 周西东 |
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Description: 君正最新CPU用户手册,MIPS平台,集合了USB,I2C,UART,LCD,SDRAM等众多接口-Jun is the latest CPU User' s Manual, MIPS platform, a collection of USB, I2C, UART, LCD, SDRAM, and many other interfaces
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Size: 1537024 |
Author: allen |
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Description: Virtex-5 FPGA实现的高性能 DDR2 SDRAM数据采集,需要对V5有一定基础的人学习-Virtex-5 FPGA DDR2 SDRAM to achieve high-performance data acquisition, the need for V5 have to learn some basic
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Size: 436224 |
Author: apple_rao |
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Description: ALTERA SDR SDRAM controller 说明文档(Altera SDR SDRAM Controller pdf)
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Size: 702464 |
Author: fsc
|
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