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[Other resource] Example-b3-1

Description: 使用Quartus II设计FPGA的应用设计实例  “\\Example-b3-1\\uart_regs\\src”目录下为设计源文件  “\\Example-b3-1\\uart_regs\\core”目录下为Altera的IP宏功能模块  “\\Example-b3-1\\uart_regs\\sim\\funcsim”目录下为功能仿真文件  “\\Example-b3-1\\uart_regs\\sim\\parsim”目录下为时序仿真文件  “\\Example-b3-1\\uart_regs\\dev”目录下为工程文件（包含了约束、综合、布局布线的过程文件和结果文件）
Platform: | Size: 397883 | Author: king | Hits:

[Communication] ofdm-sim-by-mit-and-stanford

Description: OFDM系统的自适应比特加载和功率分配程序，运行OFDM.M-OFDM system of adaptive bit load and power distribution, the running OFDM.M
Platform: | Size: 184320 | Author: 焦嘟嘟 | Hits:

[VHDL-FPGA-Verilog] Example-b3-1

Description: 使用Quartus II设计FPGA的应用设计实例  “\Example-b3-1\uart_regs\src”目录下为设计源文件  “\Example-b3-1\uart_regs\core”目录下为Altera的IP宏功能模块  “\Example-b3-1\uart_regs\sim\funcsim”目录下为功能仿真文件  “\Example-b3-1\uart_regs\sim\parsim”目录下为时序仿真文件  “\Example-b3-1\uart_regs\dev”目录下为工程文件（包含了约束、综合、布局布线的过程文件和结果文件）
Platform: | Size: 397312 | Author: king | Hits:

[VHDL-FPGA-Verilog] SVPWM

Description: 这是一个对电机进行SVPWM调速控制的VHDL源代码程序,包括了rtl主程序和测试sim仿真程序-This is a motor SVPWM Speed VHDL source code control procedures, including the main program and test rtl simulation program sim
Platform: | Size: 13312 | Author: 杨国超 | Hits:

[VHDL-FPGA-Verilog] Counter_VhdlCode

Description: it is a simple counter written in vhdl , can be simulated using model sim worked on xillinx for fpga.
Platform: | Size: 1024 | Author: aya | Hits:

[Other] sim

Description: fpga ddr_controller-fpga ddr_controller..................
Platform: | Size: 370688 | Author: guanchunjian | Hits:

[Crack Hack] pka_engine

Description: rsa ecc加速器源码和仿真环境，用于fpga-rsa ecc rtl and sim
Platform: | Size: 7987200 | Author: zhaop | Hits:

[VHDL-FPGA-Verilog] BT1120编解码时序量产代码

Description: BT1120 模块化代码，共享给大家，需要FPGA 实现BT1120 编码或者解码功能绝对有用，包含编码、解码、仿真文件(BT1120 encode & BT1120 decode & sim)
Platform: | Size: 4096 | Author: tianson | Hits:

[VHDL-FPGA-Verilog] sobel

Description: 由Verilog编写在FPGA实现sobel算法应用于图像边缘检测，工程文件可在quartus13.1以上版本打开；工程使用到ram、fifo、pll三种ip核，design文件夹下包含ram、fifo、vga控制以及串口收发和sobel算法模块，sim和doc文件夹下分别包含modelsim的仿真模块和仿真结果；测试时将200*200分辨率的图片用matlab文件夹下的matlab脚本压缩、二值化，再将生成文件中数据用串口发给FPGA，边缘检测结果会通过VGA输出。(Written by Verilog in the FPGA implementation sobel algorithm applied to the edge detection of the image, the project file can be opened in the quartus13.1 or later project use ram, fifo, pll three ip kernel, design folder contains ram, fifo, vga control and Serial port transceiver and sobel algorithm module, sim and doc folder, respectively, include modelsim simulation module and simulation results test will be 200* 200 resolution picture matlab folder under the matlab script compression, binarization, and then generated Data in the file with the serial port to the FPGA, edge detection results will be output through the VGA.)
Platform: | Size: 10222592 | Author: 丶大娱乐家 | Hits:

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