Search - SINE WAVE GENERATOR VHDL CODE

[VHDL-FPGA-Verilog] 8bitsine

Description: 8bit采样sine波形发生器,一共两个文件，各自用VHDL和VERILOG编写，通信开发平台专用-8bit sampling sine wave generator, a total of two papers, each with VHDL and VERILOG preparation, communications development platform dedicated
Platform: | Size: 5120 | Author: 王刚 | Hits:

[Embeded-SCM Develop] ad9851-1

Description:
Platform: | Size: 590848 | Author: 两鬓 | Hits:

[assembly language] sine

Description: 用verilog语言编的正弦波发生器，可以用QuartusII来打开这个源码，也可以转换成VHDL语言-Verilog language prepared by the sine wave generator can be used QuartusII to open the source code can also be converted into VHDL language
Platform: | Size: 104448 | Author: 雨孩 | Hits:

[SCM] wave-generator

Description: 产生方波，三角波，正弦波，余弦波等波形，并且可以自由选择和切换，最后可以用于波形输出-Have a square wave, triangle wave, sine wave, cosine wave, such as waveform, and can freely choose and switch, and finally can be used for waveform output
Platform: | Size: 6144 | Author: 周易 | Hits:

[VHDL-FPGA-Verilog] VHDL-ROM4

Description: 基于ROM的正弦波发生器的设计：1.正弦发生器由波形数据存储模块（ROM），波形发生器控制模块及锁存模块组成 2.波形数据存储模块（ROM）定制数据宽度为8，地址宽度为6，可存储 64点正弦波形数据，用MATLAB求出波形数据。 3.将50MHz作为输入时钟。 -ROM-based design of the sine wave generator: 1. Sinusoidal waveform generator by the data storage module (ROM), waveform generator control module and latch module 2. Waveform data storage module (ROM) custom data width of 8 , address width of 6, can store 64 points sinusoidal waveform data, waveform data are obtained using MATLAB. 3. To 50MHz clock as input.
Platform: | Size: 98304 | Author: 宫逢源 | Hits:

[Other] bxfsq

Description: 波形发生器的代码，具有产生正弦波、方波、三角波的功能。-Waveform Generator code has generated sine wave, square, triangle-wave function.
Platform: | Size: 16384 | Author: 李仁刚 | Hits:

[Software Engineering] DDS-baseddesignofthesinusoidalsignalgenerator

Description: 本设计采用AT89552单片机，辅以必要的模拟电路，实现了一个基于直接数字频率合成技术(DDS)的正弦谊号发生器。设计中采用DDS芯片AD9850产生频率1KHZ~10MHZ范围内正弦波，采用功放AD811控制输出电压幅度，由单片机AT89S52控制调节步进频率1HZ。在此基础上，用模拟乘法器MC1496实现了正弦调制信号频率为1KHZ的模拟相度调制信号；用FPGA芯片产生二进制NRZ码,与AD9850结合实现相移键控PSK、幅移键控ASK、频移镇键FSK。-AT89552 the single-chip design, supplemented by the necessary analog circuits, based on the realization of a direct digital frequency synthesis (DDS) generator of sinusoidal No. Friends. The design of DDS chip AD9850 produced using 1KHZ ~ 10MHZ frequency range of sine wave, the AD811 control amplifier output voltage range of from single-chip AT89S52-conditioning step frequency control 1HZ. On this basis, the use of analog multiplier MC1496 has sinusoidal frequency modulation signal 1KHZ degree analog phase modulated signal generated by FPGA chip NRZ binary code, combined with the AD9850 to achieve phase shift keying PSK, ASK ASK, frequency Shift key town of FSK.
Platform: | Size: 208896 | Author: 何蓓 | Hits:

[VHDL-FPGA-Verilog] Sinewave

Description: vhdl code for sine wave generator
Platform: | Size: 1024 | Author: Sreekumar Sreenivas | Hits:

[VHDL-FPGA-Verilog] ROM_based_sine_wave_generator_VHDL_design

Description: VHDL基于ROM的正弦波发生器的设计的实验报告，内附源代码-ROM-based sine wave generator VHDL design of experiment reports, included the source code
Platform: | Size: 4096 | Author: CXJ | Hits:

[Other] sine_package_256

Description: sine wave generator in VHDL code
Platform: | Size: 1024 | Author: abou_kartouna | Hits:

[VHDL-FPGA-Verilog] Miniproject_DSF_BATCH-30

Description: source code for Sine wave generator using FPGA VHDL -source code for Sine wave generator using FPGA VHDL
Platform: | Size: 834560 | Author: SKA | Hits:

[VHDL-FPGA-Verilog] VHDL

Description: VHDL设计的相关实验，包括4位可逆计数器，4位可逆二进制代码－格雷码转换器设计、序列检测器的设计、基于ROM的正弦波发生器的设计、数字密码锁的设计与实现。-VHDL design of experiments, including four reversible counters, four reversible binary code- Gray code converter design, the sequence detector design, the ROM-based sine wave generator design, digital lock design and implementation.
Platform: | Size: 49152 | Author: 张联合 | Hits:

[VHDL-FPGA-Verilog] vhdl-code-for-sine-wave-generator

Description: it is a simple code in vhdl for sine wave generator. the test bench code is also provided in ths code
Platform: | Size: 21504 | Author: nasimus | Hits:

[VHDL-FPGA-Verilog] VHDL-node

Description: VHDL的一些实验代码，其中有4位可逆计数器，4位可逆二进制代码－格雷码转换器设计、序列检测器的设计、基于ROM的正弦波发生器的设计、数字密码锁的设计与实现-Some experiments of VHDL code, which has four reversible counters, four reversible binary code- Gray code converter design, sequence detection Design, ROM-based sine wave generator design, digital design and implementation of lock
Platform: | Size: 49152 | Author: 张联合 | Hits:

[Software Engineering] sin

Description: vhdl语言写的基于rom的正弦波发生器，包含代码和仿真图-VHDL language used to write rom-based sine wave generator contains code and simulation Figure
Platform: | Size: 71680 | Author: 张瑞萌 | Hits:

[Windows Develop] SineGen

Description: Basic VHDL code to create a sine wave generator for an FPGA board.
Platform: | Size: 3072 | Author: Joe | Hits:

[VHDL-FPGA-Verilog] VHDL

Description: 正弦波发生器代码VHDL 其中包括分频正弦波数据-Sine wave generator VHDL code Divide the sine wave data including
Platform: | Size: 7168 | Author: 123456789 | Hits:

[Other Embeded program] sin

Description: 这是一个基于vhdl编写的正弦信号发生器，实现的功能为发生正弦波，给dac 0832采样-This is a sine signal generator based on VHDL code, realize the function of sine wave, give dac 0832 samples
Platform: | Size: 318464 | Author: 薛冰 | Hits:

[VHDL-FPGA-Verilog] boxingfashengqi

Description: 波形发生器的源代码，有正弦波，三角波，锯齿波，方波。modelsim仿真，包含testbench仿真代码，testbench用的verilog编写，波形发生器源代码用的VHDL编写。-Waveform generator source code, sine, triangle, sawtooth, square wave. modelsim simulation, testbench simulation code contains, verilog write testbench use, waveform generator VHDL source code used to write.
Platform: | Size: 4753408 | Author: hbxgwjl | Hits:

Category

Source Code

Web/Internet

Develop Tools

Document

Other

Search in results

OS

Platform

Language

File Type

Search list

[VHDL-FPGA-Verilog] 8bitsine

[Embeded-SCM Develop] ad9851-1

[assembly language] sine

[SCM] wave-generator

[VHDL-FPGA-Verilog] VHDL-ROM4

[Other] bxfsq

[Software Engineering] DDS-baseddesignofthesinusoidalsignalgenerator

[VHDL-FPGA-Verilog] Sinewave

[VHDL-FPGA-Verilog] ROM_based_sine_wave_generator_VHDL_design

[Other] sine_package_256

[VHDL-FPGA-Verilog] Miniproject_DSF_BATCH-30

[VHDL-FPGA-Verilog] VHDL

[VHDL-FPGA-Verilog] vhdl-code-for-sine-wave-generator

[VHDL-FPGA-Verilog] VHDL-node

[Software Engineering] sin

[Windows Develop] SineGen

[VHDL-FPGA-Verilog] VHDL

[Other Embeded program] sin

[VHDL-FPGA-Verilog] boxingfashengqi

CodeBus www.codebus.net