Search - SPI interface in VHDL

[Other] spi

Description: VHDL 实现的SPI接口，在Altera EMP7128 上应用过-VHDL SPI interface, the application of Altera EMP off
Platform: | Size: 1024 | Author: 陈同 | Hits:

Description: SPI(serial port interface)的Verilog/VHDL源代碼，已模擬並驗證。-SPI (serial port interface) of the Verilog/VHDL source code, has been simulated and verified.
Platform: | Size: 116736 | Author: hcjian | Hits:

[VHDL-FPGA-Verilog] spi

Description: 用vhdl编写的spi接口程序，在epm7128上仿真成功。-VHDL prepared using spi interface program, in the simulation epm7128 success.
Platform: | Size: 1024 | Author: 邓立新 | Hits:

[VHDL-FPGA-Verilog] PicoBlaze_amp_adc

Description: PicoBlaze 处理器放大器和 A/D 转换器控制器展示了 Linear Technology LTC6912-1 可编程增益放大器和 Linear Technology LTC1407A 模数（A/D）转换器的基本操作。结果如字符 LCD 屏幕所示。利用 PicoBlaze 处理器控制器与放大器、A/D 转换器和 LCD 屏幕进行基于 SPI 的通信。-PicoBlaze processor amplifier and A/D converter controller demonstrated the Linear Technology LTC6912-1 programmable gain amplifiers, and Linear Technology LTC1407A modulus (A/D) converter basic operation. The result was as shown in character LCD screen. Use PicoBlaze processor controller and amplifier, A/D converter and SPI-based LCD screen communication.
Platform: | Size: 1906688 | Author: andy qe | Hits:

[VHDL-FPGA-Verilog] spi

Description: 一篇比较好的spi接口的vhdl实现的参考-A relatively good spi interface realize VHDL reference
Platform: | Size: 18432 | Author: 杨子树 | Hits:

[VHDL-FPGA-Verilog] SPI_Interface

Description: SPI接口的vhdl代码，可以实现与单片机的spi通信，完整的工程-SPI interface of the VHDL code can be achieved with SCM spi communication, complete works
Platform: | Size: 4096 | Author: wanyou2345 | Hits:

[VHDL-FPGA-Verilog] SimpleSpi

Description: SPI接口VHDL代码,内有说明,很详细.-SPI interface VHDL code, which has made it clear that, in great detail.
Platform: | Size: 180224 | Author: dushibiao | Hits:

[VHDL-FPGA-Verilog] VHDL-SPI-Module.doc

Description: 本spi参数化通讯模块是一个支持SPI串行通信协议从协议的SPI从接口。可通过改变参数设置传输的位数，由外部控制器给定脉冲控制传输。-The parameters of spi communication module is a support SPI serial communication protocol from the agreement from the SPI interface. By changing the parameter settings can be transmitted over the median, given by an external controller to control transmission pulse.
Platform: | Size: 37888 | Author: | Hits:

[VHDL-FPGA-Verilog] LPC2DDR2

Description: Module Function Description: This module allows a SPI ROM to be used in a LX/CS5536 system. Details are below: 1.Provide a memory window to the SPI EPROM at FFF80000h-FFFFFFFFh (512KB). 2.Provide an interface to the SPI bus to allow the SPI EPROM to be programmed. 3.Support DDR2 memory initial process. 4.Support LPC/SPI ROM switch using Hardware pin selection and Software setting method 5.Support LPC Memory Read/Write, LPC I/O Read/Write 6.Support SPI Chip Erase/Byte Program/Write Status/Read Status/Read Array -Module Function Description: This module allows a SPI ROM to be used in a LX/CS5536 system. Details are below: 1.Provide a memory window to the SPI EPROM at FFF80000h-FFFFFFFFh (512KB). 2.Provide an interface to the SPI bus to allow the SPI EPROM to be programmed. 3.Support DDR2 memory initial process. 4.Support LPC/SPI ROM switch using Hardware pin selection and Software setting method 5.Support LPC Memory Read/Write, LPC I/O Read/Write 6.Support SPI Chip Erase/Byte Program/Write Status/Read Status/Read Array
Platform: | Size: 8192 | Author: 吴羽中 | Hits:

[Embeded-SCM Develop] SPI_TEST

Description: The Serial Peripheral Interface Bus or SPI bus is a synchronous serial data link standard named by Motorola that operates in full duplex mode. Devices communicate in master/slave mode where the master device initiates the data frame. Multiple slave devices are allowed with individual slave select (chip select) lines. Sometimes SPI is called a "four wire" serial bus, contrasting with three, two, and one wire serial buses.-The Serial Peripheral Interface Bus or SPI bus is a synchronous serial data link standard named by Motorola that operates in full duplex mode. Devices communicate in master/slave mode where the master device initiates the data frame. Multiple slave devices are allowed with individual slave select (chip select) lines. Sometimes SPI is called a "four wire" serial bus, contrasting with three, two, and one wire serial buses.
Platform: | Size: 478208 | Author: wei | Hits:

[VHDL-FPGA-Verilog] vspi

Description: 一个用vhdl语言写的spi接口实例，经过altera的fpga测试可以使用。-Written in a language with vhdl spi interface to an instance, after the fpga altera test can be used.
Platform: | Size: 6144 | Author: tofly | Hits:

[VHDL-FPGA-Verilog] SD_SPI

Description: sd卡spi接口的verilog程序，quartus2,全部调好能已经应用于SD卡模块。-sd card spi interface verilog program, quartus2, all tuned to have been used in SD card module.
Platform: | Size: 2700288 | Author: 洪传荣 | Hits:

[VHDL-FPGA-Verilog] SPI

Description: VHDL语言编写的SPI通信接口,可实现与单片机等外部MCU的通信,且只占用较少的引脚线-Written in VHDL SPI communication interface, can be realized with the microcontroller and other external MCU communication, and only takes less pin line
Platform: | Size: 585728 | Author: ldong1989 | Hits:

[VHDL-FPGA-Verilog] DigipotDriver

Description: VHDL to use as AD5204 (4-Channel Digital Potentiometer) control driver. SPI interface. Instantiable in any platform.
Platform: | Size: 3072 | Author: Marc | Hits:

[VHDL-FPGA-Verilog] xapp386

Description: This document details the VHDL implementation of a Serial Peripheral Interface (SPI) master in a Xilinx® CoolRunner™ -II CPLD. CoolRunner-II CPLDs are the lowest power CPLDs available, making this the perfect target device for an SPI Master.-This document details the VHDL implementation of a Serial Peripheral Interface (SPI) master in a Xilinx® CoolRunner™ -II CPLD. CoolRunner-II CPLDs are the lowest power CPLDs available, making this the perfect target device for an SPI Master.
Platform: | Size: 194560 | Author: hamed | Hits:

[VHDL-FPGA-Verilog] xapp348

Description: This document details the VHDL implementation of a Serial Peripheral Interface (SPI) master in a Xilinx CoolRunner™ XPLA3 CPLD.-This document details the VHDL implementation of a Serial Peripheral Interface (SPI) master in a Xilinx CoolRunner™ XPLA3 CPLD.
Platform: | Size: 119808 | Author: hamed | Hits:

[VHDL-FPGA-Verilog] spi_verilog_master_slave_latest.tar

Description: 该项目从需要具有强大而简单的以VHDL编写的SPI接口核心开始，用于通用的FPGA到设备接口。所产生的内核产生小而高效的电路，从非常慢的SPI时钟到超过50MHz的SPI时钟。-This project started the need to have robust yet simple SPI interface cores written in VHDL to use in generic FPGA-to-device interfacing. The resulting cores generate small and efficient circuits, that operate very slow SPI clocks up to over 50MHz SPI clocks.
Platform: | Size: 3072 | Author: asdtgg | Hits:

[VHDL-FPGA-Verilog] verilog_spi-master

Description: verilog_spi A simple demo SPI interface implemented in verilog
Platform: | Size: 6144 | Author: d.pershin | Hits:

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[Other] spi

[VHDL-FPGA-Verilog] spi.tar

[VHDL-FPGA-Verilog] spi

[VHDL-FPGA-Verilog] PicoBlaze_amp_adc

[VHDL-FPGA-Verilog] spi

[VHDL-FPGA-Verilog] SPI_Interface

[VHDL-FPGA-Verilog] SimpleSpi

[VHDL-FPGA-Verilog] VHDL-SPI-Module.doc

[VHDL-FPGA-Verilog] LPC2DDR2

[Embeded-SCM Develop] SPI_TEST

[VHDL-FPGA-Verilog] vspi

[VHDL-FPGA-Verilog] SD_SPI

[VHDL-FPGA-Verilog] SPI

[VHDL-FPGA-Verilog] DigipotDriver

[VHDL-FPGA-Verilog] xapp386

[VHDL-FPGA-Verilog] xapp348

[VHDL-FPGA-Verilog] spi_verilog_master_slave_latest.tar

[VHDL-FPGA-Verilog] verilog_spi-master

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