Search - SPI master verilog

Search - SPI master verilog - List

[VHDL-FPGA-Verilog] bfm DL : 0: Verilog HDL编写的总线功能模型，十分有用，需要的下载-Verilog HDL prepared by the bus functional model is useful, it needs to download
Update : 2025-02-17 Size : 2kb Publisher : wyl
[VHDL-FPGA-Verilog] SimpleSpi DL : 0: master spi的源代码（verilog），包括文档，测试程序-master spi the source code (verilog), including documentation, testing procedures
Update : 2025-02-17 Size : 176kb Publisher : wood
[VHDL-FPGA-Verilog] spi_op_core DL : 1: 串行数据SPI master的开源控制器，verilog，内附说明-SPI master serial data open-source controller, verilog, containing a description
Update : 2025-02-17 Size : 80kb Publisher : 王天
[SCM] mcu-cpld-spi DL : 0: mcu与cpld之间spi接口程序，mcu为master，cpld用verilog写成slave模块-mcu with spi interface program between the CPLD, mcu for the master, cpld written using Verilog slave module
Update : 2025-02-17 Size : 108kb Publisher : 叶灿
[Com Port] pwm16bits DL : 0: SPI总线Master的verilog代码-SPI Bus Master of Verilog code
Update : 2025-02-17 Size : 1kb Publisher : xudong
[Com Port] spi DL : 0: SPI master的verilog代码-Verilog code for SPI master
Update : 2025-02-17 Size : 2kb Publisher : xudong
[Other] spi.tar DL : 0: This is a verilog code used oversampled clock to implement SPI slave. Also include C code for a ARM processor as the SPI master-This is a verilog code used oversampled clock to implement SPI slave
Update : 2025-02-17 Size : 1kb Publisher : johnl
[MPI] spi_verilog DL : 0: 实现SPI MASTER功能，并有仿真代码和仿真结果。-To achieve SPI MASTER function, and a simulation code and simulation results.
Update : 2025-02-17 Size : 44kb Publisher : davi_insist
[VHDL-FPGA-Verilog] SpiMaster DL : 0: This a verilog code for SPI Master testbench is also provided spi_top.v Xilinx ISE or Icarus verilog to compile and simulate-This is a verilog code for SPI Master testbench is also provided spi_top.v Xilinx ISE or Icarus verilog to compile and simulate
Update : 2025-02-17 Size : 9kb Publisher : RutaliMulye
[VHDL-FPGA-Verilog] spi DL : 0: SPI总线接口的verilog源码，包含仿真模块modelsim 和 quartus 工程。本人测试通过。-SPI bus interface in verilog source code, including the simulation module modelsim and quartus project. I test.
Update : 2025-02-17 Size : 284kb Publisher : 阿虎
[VHDL-FPGA-Verilog] modelsim DL : 0: verilog SPI master 的完整实验报告仅供参考切勿抄袭-verilog SPI master
Update : 2025-02-17 Size : 44kb Publisher : ying ma
[VHDL-FPGA-Verilog] SPI_Master DL : 0: verilog HDL 语言描述的8位并行转SPI程序-verilog HDL language description of the 8-bit parallel transfer SPI program
Update : 2025-02-17 Size : 1kb Publisher :
[VHDL-FPGA-Verilog] spi-master DL : 1: code for Master side
Update : 2025-02-17 Size : 119kb Publisher : suni
[VHDL-FPGA-Verilog] SPI-Master-master DL : 0: Use code for Maser SPI
Update : 2025-02-17 Size : 12kb Publisher : suni
[VHDL-FPGA-Verilog] SPI_master DL : 0: spi-master模块的verilog(simple program for SPI-Master)
Update : 2025-02-17 Size : 1kb Publisher : jxls378816
[VHDL-FPGA-Verilog] Nitro-Parts-lib-SPI-master DL : 0: Nitro-Parts-lib-SPI Verilog SPI master and slave
Update : 2025-02-17 Size : 5kb Publisher : d.pershin
[Com Port] Master SPI的Verilog源代码(包括文档测试程序) DL : 1: SPI接口的从机实现（利用verilog HDL语言）(Slave implementation of SPI interface (using Verilog HDL language))
Update : 2025-02-17 Size : 181kb Publisher : 够歇斯底里吗
[VHDL-FPGA-Verilog] spi master slave DL : 0: SPI master slave (fpga/verilog)
Update : 2025-02-17 Size : 66kb Publisher : taso999
[Other] spi_verilog_master_slave_latest.tar DL : 0: spi 的verilog rtl 代码, 包括整体仿真环境，测试码等(spi master or slave verilog rtl code)
Update : 2025-02-17 Size : 3kb Publisher : jekky888888
[Other] spi_masterSPI Master 的Verilog源代码 DL : 0: 实现SPI主站通信功能,感兴趣的可以下载。(spi master use verilog.)
Update : 2025-02-17 Size : 130kb Publisher : wenyiwenni

« 12 3 »