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[VHDL-FPGA-Verilog] vhdl平方根

Description: 计算某数的平方根，VHDL语言，使用简单-calculate the square root of a number, VHDL, use simple
Platform: | Size: 39936 | Author: wl | Hits:

[Embeded-SCM Develop] fsqr

Description: 功能：浮点数开平方（快速逼近算法） 入口条件：操作数在[R0]中。 出口信息：OV=0时，平方根仍在[R0]中，OV=1时，负数开平方出错。 影响资源：PSW、A、B、R2～R7 堆栈需求： ２字节 -Features: Floating-point square root (fast approximation algorithm) entrance conditions: operand in [R0] in. Export information: OV = 0 when the square root is still [R0] in, OV = 1, the negative square root error. The impact of resources: PSW, A, B, R2 ~ R7 Stack requirements: 2 bytes
Platform: | Size: 4096 | Author: kos | Hits:

[SCM] AVR_Fixed_Point_Library

Description: AVR单片机定点计算函数说明及C源码。包括定点求解平方根和对数。还打包了一个外国网站上的Fixed Point Library。定将给开发工作带来极大的方便。-AVR single-chip fixed-point calculation function descriptions and C source code. Including fixed-point solution of the square root and logarithmic. Also packed a foreign site on the Fixed Point Library. Scheduled development work will bring great convenience.
Platform: | Size: 1906688 | Author: 温漠洲 | Hits:

[Communication-Mobile] pppp

Description: 求平方根升余弦滤波器系数的程序-For the square root raised cosine filter coefficients of the procedures
Platform: | Size: 1024 | Author: haoshilin | Hits:

[VHDL-FPGA-Verilog] sqrt

Description: verilog 硬件平方根算法 采用与笔算平方根一样的算法-Verilog hardware and written calculation algorithm uses the square root of the square root of the same algorithm
Platform: | Size: 17408 | Author: lizhizhou | Hits:

[VHDL-FPGA-Verilog] ref-sqroot

Description: 開平方根IP將sqroot_license.txt中的FEATURE 6AF8_0048 alterad 0000.00 permanent uncounted 4A689178551B VENDOR_STRING=gl15kdhm5gUPkJD7iM82mn$$ HOSTID=ANY加入就可以使用了！-The square root of IP will be open sqroot_license.txt in FEATURE 6AF8_0048 alterad 0000.00 permanent uncounted 4A689178551B VENDOR_STRING = gl15kdhm5gUPkJD7iM82mn $ $ HOSTID = ANY can be used to join!
Platform: | Size: 39936 | Author: lin | Hits:

[VHDL-FPGA-Verilog] pre_norm_sqrt

Description: 一种用VHDL语言描述的浮点平方根前规格化的源代码编程-VHDL language used to describe a floating-point square root of the source code before the standardized programming
Platform: | Size: 2048 | Author: zhshup | Hits:

[Other] commdoc_rrc

Description: Modify the Gray-coded modulation example (COMMDOC_GRAY) so that it uses a pair of square root raised cosine filters to perform pulse shaping and matched filtering at the transmitter and receiver, respectively.-Modify the Gray-coded modulation example (COMMDOC_GRAY) so that it uses a pair of square root raised cosine filtersto perform pulse shaping and matched filtering at thetransmitter and receiver, respectively.
Platform: | Size: 2048 | Author: JILIANGHAI | Hits:

[VC/MFC] CHOLESKY

Description: C语言利用平方根法(CHOLESKY)求解对称联立方程式-C language using the square root law (CHOLESKY) symmetric solution of simultaneous equations
Platform: | Size: 1024 | Author: hawksilent | Hits:

[matlab] Chapter_55

Description: 平方根升余弦脉冲 平方根升余弦脉冲 平方根升余弦脉冲 平方根升余弦脉冲-Square Root Raised Cosine Square Root Raised Cosine pulse Pulse Pulse square root raised cosine square root raised cosine square root raised cosine pulse Pulse Pulse square root raised cosine square root raised cosine pulse
Platform: | Size: 1024 | Author: 高翔云 | Hits:

[VHDL-FPGA-Verilog] sqrt

Description: This zip file contains the verilog source code for square root calculation and its test bench
Platform: | Size: 2048 | Author: Jaganathan | Hits:

[Communication-Mobile] qpsk_simulink

Description: In this simulink model , QPSK modulation and demodulation is simulated .A square root raised cosine pulse shaped signal is modulated and given as input to the demodulator.The received signal is demodulated and given to the detector where it is matched filtered and down-sampled .The effects of symbol timing offset can be seen by varying the phase of down-sampling operation.The signal transmitted is recovered at the detector output.-In this simulink model , QPSK modulation and demodulation is simulated .A square root raised cosine pulse shaped signal is modulated and given as input to the demodulator.The received signal is demodulated and given to the detector where it is matched filtered and down-sampled .The effects of symbol timing offset can be seen by varying the phase of down-sampling operation.The signal transmitted is recovered at the detector output.
Platform: | Size: 8192 | Author: quail | Hits:

[VHDL-FPGA-Verilog] square-root

Description: Verilog硬件描述语言能够用软件语言的的方式描述硬件特性，并可用仿真方式完成电路的调试.本文介绍了基于EasyFPGA030的开平方运算器的设计，详细说明了运用verilog语言的设计过程与实现成果。-Verilog hardware description language（HDL）specializes in describing hardware in the way of software language, and complete circuit simulation available are introduced. This thesis include the design of square root machine which is based on the EasyFPGA030 ,as well as the details of the design process Verilog language use and achieve results.
Platform: | Size: 905216 | Author: stella | Hits:

[Documents] rolloffdigitalfilterdesign

Description: 平方根升余弦滚降数字滤波器的设计 很不错的文章-Square root raised cosine roll-off digital filter design
Platform: | Size: 350208 | Author: Kevin | Hits:

[VHDL-FPGA-Verilog] sqrt_for_single_float_point

Description: 用verilog实现了基于中值定理求解单精度浮点开方的功能，希望对大家学习有所帮助-With verilog implemented based on the mean value theorem to solve single-precision floating point square root function, we want to study and help ... ...
Platform: | Size: 5120 | Author: 楚艳超 | Hits:

[Algorithm] Fast-inverse-square-root

Description: 快速求平方根的倒数的书籍，算法的介绍与详解-Fast inverse square root of books, and Detailed algorithm description
Platform: | Size: 214016 | Author: 杨阳 | Hits:

[assembly language] SQUARE-ROOT

Description: 8051 asm program for square root calculation
Platform: | Size: 1024 | Author: devakumari | Hits:

[VHDL-FPGA-Verilog] A-VHDL-Function-for-finding-SQUARE-ROOT

Description: vhdl coding for square root-vhdl coding for square root...
Platform: | Size: 3072 | Author: a.deivaseelan | Hits:

[DSP program] Square-Root-Raised-Cosine-Filter

Description: 根升余弦基带成形滤波器的设计及其DSP实现.最后利用系数对称特性，在某软件无线电电台系统的DSP 芯片中编程， 实现均方根升余弦滤波器的成形滤波算法-First this essay introduces baseband shaped filter theory and requirements of an SDR system on shaped filtering. And, the author introduces various realization methods of FIR filter presently, in addition the author expatiate on square-root raised-cosine filter and its design in IS-95 software defined system. Finally, the author illustrates the shaped filter realization based on software programming using symmetry properties of FIR filter coefficients
Platform: | Size: 117760 | Author: 程文翔 | Hits:

[Other Embeded program] a-square-root-algorithm

Description: 介绍一种高速高精度的开方算法它适用于最一般开方运算形式汉, 算法将数据映射 至（0,1000）区间, 进而将该区间进行非均匀分段, 并用查表与线性插值相结合的方法, 既实现了高速、高精度开方运算, 又使数据表格占用较少的存贮单元这种算法还很容易推广应用于其他幂函数计算-Introduced a high-speed high-precision square root algorithm, it applies to the Han Dynasty, the most general form of root operation, the algorithm maps data To (0,1000) interval, and thus the range of non-uniform segmentation, and look-up table with linear interpolation method of combining both high-speed, high-precision root operation, and data tables take up less deposit storage unit of this algorithm is very easily applied to other power function calculation
Platform: | Size: 2412544 | Author: sunshine | Hits:
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