Search - Strobe vhdl

[VHDL-FPGA-Verilog] ADcaiyang

Description: A/D采样控制模块设计 A/D采样控制模块负责控制外部ADC0809芯片多路模拟输入量的选通以及实现对A/D采样过程的合理控制。此部分的设计根据《EDA技术与VHDL》P211——P212的例8-2编写，所不同的是这里将书中“ADDA<=1”的赋值语句改为“ADDA <=EN”，EN是所设置的输入按键用来控制INO与IN1间的通道选择。 -A/D sampling control module designed A/D sampling control modules responsible for controlling external ADC0809 chip multi-channel analog input, as well as the amount of strobe to achieve A/D sampling the reasonable control of the process. This part of the design under the EDA technology and VHDL P211- P212 preparation of the cases of 8-2, the difference is that here the book ADDA <= 1 of the assignment changed to ADDA <= EN , EN is the set of input buttons used to control between INO and IN1 channel selection.
Platform: | Size: 1024 | Author: xuye | Hits:

[GIS program] register

Description: 32×32的寄存器堆，它有32个32位的寄存器、两个读端口和一个写端口。该寄存器堆由3个层次共5个模块构成，最低层次的模块是D触发器，中间层次的模块包括32位寄存器、5位地址译码器、32选1多路选通器，顶层模块是寄存器堆模块。设计采用行为建模和结构建模相结合的方法，先用行为建模方法建立低层模块，然后再用结构建模方法搭建高层模块。-32 × 32 of the register file, it has 32 32-bit registers, two read ports and one write port. The register file by the three levels of a total of five modules, the lowest level module is the D flip-flop, middle-level module including 32-bit register, address decoder 5, 32 election more than one way strobe, and top-level module is Register File module. Design using behavioral modeling and structural modeling method of combining the first act of modeling methods used to establish low-level modules, then the structural modeling method to build high-level module.
Platform: | Size: 4096 | Author: 甜 | Hits:

[VHDL-FPGA-Verilog] led_control

Description: 本实验箱采用的液晶显示屏内置的控制器为SED1520，点阵为122×32，需要两片SED1520组成，由E1，E2分别选通，以控制显示屏的左右两半屏。图形液晶显示模块有两种连接方式，一种为直接访问方式，一种为间接访问方式。本实验采用直接控制方式。直接控制方式就是将液晶显示模块的接口作为存储器或I/O设备直接挂在计算机总线上。计算机通过地址译码器控制E1和E2的选通；读/写操作信号R/W有地址线A1 控制，命令/数据寄存器选择信号由地址线A0控制。 -The experimental box with built-in LCD controller for the SED1520, lattice is 122 × 32, needs two SED1520 formed by the E1, E2, respectively gating to control the display of about two and a half screen. Graphic LCD module has two connections, one for the direct access method, an indirect access. In this study the direct control mode. Direct control method is to interface LCD module as memory or I/O devices directly linked to the computer bus. Computer controlled by address decoder strobe E1 and E2 read/write signal R/W control the address lines A1, command/data register select control signal from the address line A0.
Platform: | Size: 1206272 | Author: yangxiao | Hits:

[Other] counter_bcd7

Description: bcd十进制计数器，用于频率计设计的计数器单元，输出zeros用于选通量程使用！-bcd decimal counter, the counter for frequency counter design unit, the output zeros for the use of strobe range!
Platform: | Size: 1024 | Author: jim | Hits:

[VHDL-FPGA-Verilog] shunmaguanxianshidianlu

Description: 用VHDL语言编写一个八位数码管显示电路，每个数码管的八个段分别连在一起，八个数码管分别由八个选通信号选择。被选通的数码管显示数据，其余关闭-With the VHDL language to write a eight digital tube display circuit, each digital tube eight segments are connected together, the eight digital tube are respectively composed of eight strobe signal selection. Was selected through the digital tube display data, the remaining closed
Platform: | Size: 1024 | Author: 陈蕊 | Hits:

[VHDL-FPGA-Verilog] MUX4

Description: 本程序使用vhdl语言编写，能够在ALTERA CPLD-EPM3128A平台上模拟出一个多路数据选通器。-This program written in vhdl language, be able to simulate a multi-channel data strobe device of ALTERA CPLD-EPM3128A platform.
Platform: | Size: 79872 | Author: cheng guanghui | Hits:

[VHDL-FPGA-Verilog] 16^16dianzhen

Description: vhdl 16*16点阵板显示行扫描低电平选通-vhdl 16* 16 dot matrix board low strobe line scan
Platform: | Size: 385024 | Author: 比按 | Hits:

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