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Description: 将16位二进制有符号纯小数转换为32位单精度浮点数。实际应用时，最好加tsu、tco约束条件，速度会快些。-There will be 16-bit binary decimal symbol is converted to pure 32-bit single precision floating point. Practical applications, it is best to increase tsu, tco constraints, the speed will be faster.
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Size: 1024 |
Author: li |
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Description: 求主副测线交点差，自动判断测线相交与否，可用于物探工程-Lord Deputy measuring line intersection difference
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Size: 1024 |
Author: puzhizhou |
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Description: Cyclone™ FPGA具有锁相环（PLL）和全局时钟网络，提供完整的时钟管理方案。Cyclone PLL具有时钟倍频和分频、相位偏移、可编程占空比和外部时钟输出，进行系统级的时钟管理和偏移控制。Altera® Quartus® II软件无需任何外部器件，就可以启用Cyclone PLL和相关功能。本文将介绍如何设计和使用Cyclone PLL功能。
PLL常用于同步内部器件时钟和外部时钟，使内部工作的时钟频率比外部时钟更高，时钟延迟和时钟偏移最小，减小或调整时钟到输出（TCO）和建立（TSU）时间。
-Cyclone ™ FPGA with a phase-locked loop (PLL) and the global clock network and provide a complete clock management solution. Cyclone PLL with the clock multiplier and divider, phase offset, programmable duty cycle and the external clock output for system-level clock management and offset control. Altera ® Quartus ® II software does not require any external devices, you can enable the Cyclone PLL and related functions. This article describes how to design and use the Cyclone PLL features. PLL clock devices commonly used in the synchronization of internal and external clock, so that the inner workings of the clock frequency higher than the external clock, clock delay and clock skew minimum, reduce or adjust the clock to the output (TCO) and the establishment of (TSU) time.
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Size: 553984 |
Author: 裴雷 |
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Description: 清华大学C++全套课件 Cpp Courseware of tsu-Cpp Courseware of tsu
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Size: 552960 |
Author: 王启盛 |
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Description: AD驱动 TW2815/tw2865/TW9910/al244/sv2825
VGA驱动
TVP5715-AD driver TW2815/tw2865/TW9910/al244/sv2825 VGA driver TVP5715
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Size: 11264 |
Author: yfy |
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Description: 几篇解读FPGA内部时序问题的好文章，从最近本的Tco,Tsu，Th等入门。一直到如何对时序进行约束，如何处理各种影响FPGA时钟的因素。如何读懂时序图（Interpreting the Timing Diagram） -FPGA internal timing problems read several good articles, from the most recent of Tco, Tsu, Th and other entry. How the timing has to be constrained, how to handle a variety of factors affect the FPGA clock. How to read timing diagram (Interpreting the Timing Diagram)
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Size: 3587072 |
Author: 徐博 |
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Description: 1. Access the relevant reference books or technical data books and give accurate definitions for the following timing parameters:
(1) propagation time tPD,
(2) transition time tTD,
(3) setup time tSU,
(4) hold time tHD, and
(5) clock-to-output time tCO.
2. Compare the main features of 74-393 and 74-163 counters and construct an N-bit synchronous counter using 74-163(s).
3. Macrocells (MCs) are key components of Programmable Logic Device (PLD). Based on the MC logic schematic diagram below, please describe its functions.
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Size: 172032 |
Author: 魏攸 |
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Description: 可以自动检测软件是否要更新！！！很实用，适合新手。-Institute of field trials of new trendy Yo ! ∵ ! University Last updated !! element Tsu Nina sucking force !! Forest Alternative I Alternative . E Tsu pre-threshold
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Size: 18432 |
Author: 样丽丽 |
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Description: matlab教程r2011a+张志涌+杨祖樱
DOC版电子书
全-matlab tutorial r2011a+ Yang Tsu Ying Zhang Yong+ DOC Version eBook
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Size: 4328448 |
Author: dxin jin |
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Description: MStar TSU系列LCD monitor显示板源码，因为该系列芯片已停产，所以分享出来工大家研究-MStar TSU series LCD monitor display board source, because the chips have been discontinued, so we share out work study
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Size: 174080 |
Author: blue |
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Description: MStar TSU56AK 芯片规格书,为配合TSU系列源码而分享-MStar TSU56AK chip specifications to meet TSU series source and Share
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Size: 676864 |
Author: blue |
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Description: ACS800用户手册 ACS800-404晶闸管供电模块（TSU），详细说明硬件描述，柜体安装，程序特性，功能参数等-ACS800 User s Manual ACS800-404 thyristor power modules (TSU), a detailed description of the hardware description, cabinet installation, the program features, functions, parameters, etc.
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Size: 11268096 |
Author: 陈相逢 |
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